| Review of FinFET devices and perspective on circuit design challenges RK Maurya, B Bhowmick Silicon 14 (11), 5783-5791, 2022 | 57 | 2022 |
| Low to high-frequency noise behavior investigation of steeper sub-threshold swing NC-GeFinFET RK Maurya, R Saha, B Bhowmick Microelectronics Journal 131, 105642, 2023 | 13 | 2023 |
| Negative capacitance gate-all-around PZT silicon nanowire with high-K/metal gate MFIS structure for low SS and high I on/I off V Kumar, RK Maurya, G Rawat, K Mummaneni Semiconductor Science and Technology 38 (5), 055018, 2023 | 7 | 2023 |
| Effect of curie temperature on electrical parameters of NC-FinFET and digital switching application of NC-FinFET RK Maurya, V Kumar, R Saha, B Bhowmick Microelectronics Journal 139, 105892, 2023 | 6 | 2023 |
| Performance optimization of high-K GAA-PZT Negative Capacitance FET MFIS Silicon Nanowire for low power RFIC and analog applications V Kumar, RK Maurya, G Rawat, K Mummaneni Physica Scripta 98 (11), 115029, 2023 | 5 | 2023 |
| Enhanced Magnetic Field Sensing with MAGNC-FinFET: A Current Mode Hall Effect Approach RK Maurya, RG Debnath, R Saha, B Bhowmick IEEE Transactions on Nanotechnology, 2024 | 2 | 2024 |
| Effects of fitting parameter on device performance and reliability of double-gate n-finfet by using bohm quantum potential (bqp) model RK MAURYA, B Bhowmick | 2 | 2022 |
| Design of high-speed 32-bit vedic multiplier using verilog hdl H Ganji, RK Maurya, K Mummaneni Micro and Nanoelectronics Devices, Circuits and Systems: Select Proceedings …, 2022 | 2 | 2022 |
| Effects of the remnant polarization on the electrical characteristics of steeper sub-threshold swing Fe-GeFinFET RK Maurya, V Kumar, R Saha, B Bhowmick Materials Science and Engineering: B 303, 117317, 2024 | 1 | 2024 |
| Effects of Ferro-thickness and Temperature on Electrical Performance of Si:HfO2 based NC-FinFET RK Maurya, V Kumar, R Saha, B Bhowmick 2023 11th International Symposium on Electronic Systems Devices and …, 2023 | 1 | 2023 |
| Oxide and ferro layer thickness optimization of negative capacitance junctionless VSTB FET to improve electrical and thermal noise performance RK Maurya, V Kumar, RG Devnath, R Saha, B Bhowmick Materials Science and Engineering: B 309, 117626, 2024 | | 2024 |
| Impact of source/drain lateral straggle on GIDL current of low SS NC-FinFET RK Maurya, V Kumar, R Saha, B Bhowmick International Journal of Electronics, 1-19, 2024 | | 2024 |
| N-DIBL optimization of NC-GAAFET NW for low power fast switching applications V Kumar, RK Maurya, K Mummaneni Microelectronics Journal 151, 106321, 2024 | | 2024 |
| Temperature analysis of lead zirconate titanate GAA-NCFET nanowire with interface trap charges V Kumar, RK Maurya, K Mummaneni Materials Science and Engineering: B 307, 117523, 2024 | | 2024 |
| A novel dual-gate negative capacitance TFET for highly sensitive label free biosensing RK Maurya, RG Debnath, AK Yadav, B Bhowmick Semiconductor Science and Technology 39 (9), 095010, 2024 | | 2024 |
| Noise analysis of NC-GAAFET cylindrical nanowire with non-uniform interface trap charge V Kumar, RK Maurya, G Rawat, RG Debnath, K Mummaneni Physica Scripta 99 (7), 075048, 2024 | | 2024 |
