| Vertical interconnects of microbumps in 3D integration C Chen, D Yu, KN Chen MRS bulletin 40 (3), 257-263, 2015 | 89 | 2015 |
| Reliability evaluation of a CoWoS-enabled 3D IC package B Banijamali, CC Chiu, CC Hsieh, TS Lin, C Hu, SY Hou, S Ramalingam, ... 2013 IEEE 63rd Electronic Components and Technology Conference, 35-40, 2013 | 68 | 2013 |
| Array antenna integrated fan-out wafer level packaging (InFO-WLP) for millimeter wave system applications CH Tsai, JS Hsieh, M Liu, EH Yeh, HH Chen, CW Hsiao, CS Chen, CS Liu, ... 2013 IEEE International Electron Devices Meeting, 25.1. 1-25.1. 4, 2013 | 57 | 2013 |
| 300mm size ultra-thin glass interposer technology and high-Q embedded helical inductor (EHI) for mobile application WC Lai, HH Chuang, CH Tsai, EH Yeh, CH Lin, TH Peng, LJ Yen, ... 2013 IEEE International Electron Devices Meeting, 13.4. 1-13.4. 4, 2013 | 32 | 2013 |
| Wafer level integration of an advanced logic-memory system through 2ndgeneration CoWoS® technology WC Chen, C Hu, KC Ting, V Wei, TH Yu, SY Huang, VCY Chang, ... 2017 Symposium on VLSI Technology, T54-T55, 2017 | 28 | 2017 |
| A manufacturable interposer MIM decoupling capacitor with robust thin high-K dielectric for heterogeneous 3D IC CoWoS wafer level system integration WS Liao, CH Chang, SW Huang, TH Liu, HP Hu, HL Lin, CY Tsai, CS Tsai, ... 2014 IEEE International Electron Devices Meeting, 27.3. 1-27.3. 4, 2014 | 24 | 2014 |
| High performance passive devices for millimeter wave system integration on integrated fan-out (InFO) wafer level packaging technology CH Tsai, JS Hsieh, WH Lin, LJ Yen, JN Hung, TH Peng, HC Wang, ... 2015 IEEE International Electron Devices Meeting (IEDM), 25.2. 1-25.2. 4, 2015 | 20 | 2015 |
| 3D IC heterogeneous integration of GPS RF receiver, baseband, and DRAM on CoWoS with system BIST solution WS Liao, HN Chen, KK Yen, EH Yeh, FW Kuo, TJ Yeh, F Kuo, CP Jou, ... 2013 Symposium on VLSI Circuits, C18-C19, 2013 | 17 | 2013 |
| High-performance inductors for integrated fan-out wafer level packaging (InFO-WLP) SM Chen, LH Huang, JH Yeh, YJ Lin, FW Kuo, HN Chen, MY Chiu, ... 2013 Symposium on VLSI Technology, T46-T47, 2013 | 11 | 2013 |
| A high-performance low-cost chip-on-Wafer package with sub-μm pitch Cu RDL WS Liao, CC Chiang, WM Wu, CH Fan, SL Chiu, CC Chiu, TY Chen, ... 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical …, 2014 | 10 | 2014 |
| High Q-factor 3D Solenoid Inductor on InFO Package for RF System Integration TC Tang, CC Lin, CW Hsu, CL Lu, CH Tsai, KC Wu, HP Pu, CS Liu, ... 2019 Electrical Design of Advanced Packaging and Systems (EDAPS), 1-3, 2019 | 6 | 2019 |
| Lead-free flip chip solution for 40 nm extreme low-k interconnect system SY Hou, CW Shih, WC Wu, CH Hsieh, AJ Su, CH Tung, SP Jeng, MJ Li, ... 2010 IEEE International Interconnect Technology Conference, 1-3, 2010 | 6 | 2010 |
| Integrated Fan‐Out (InFO) for High Performance Computing DCH Yu, J Yeh, KC Yee, CH Tung Embedded and Fan‐Out Wafer and Panel Level Packaging Technologies for …, 2022 | 3 | 2022 |
| Thin die fabrication and applications to wafer level system integration DCH Yu, WC Chiou, CH Tung Materials for Advanced Packaging, 237-285, 2017 | 2 | 2017 |
| Integrated Fan‐Out (InFO) for Mobile Computing DCH Yu, J Yeh, KC Yee, CH Tung Embedded and Fan‐Out Wafer and Panel Level Packaging Technologies for …, 2022 | 1 | 2022 |
| From VLSI to WLSI an introduction to 3D wafer level system integration CH Tung, D Yu 2015 IEEE 22nd International Symposium on the Physical and Failure Analysis …, 2015 | | 2015 |
| Taper pad design to improve electrical performance of BGAs on wafer level package (WLP) CH Tsai, V Yeh, CT Wang, D Yu 2012 IEEE Electrical Design of Advanced Packaging and Systems Symposium …, 2012 | | 2012 |
