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Rittik Ghosh
Rittik Ghosh
PhD researcher, Institute for Microelectronics, TU Wien
在 iue.tuwien.ac.at 的电子邮件经过验证
标题
引用次数
引用次数
年份
Design and investigation of InAs source dual metal stacked gate-oxide heterostructure tunnel FET based label-free biosensor
R Ghosh, RP Nelapati
Micro and Nanostructures 174, 207444, 2023
122023
Investigation of gate-engineered heterostructure tunnel field effect transistor as a label-free biosensor: a compact study
R Ghosh, A Karmakar, P Saha
Applied Physics A 129 (2), 94, 2023
102023
Performance investigation of dual trench split-control-gate MOSFET as hydrogen gas sensor: A catalytic metal gate approach
R Ghosh
IEEE Sensors Letters 7 (5), 1-4, 2023
92023
Impact of Deep Cryogenic Temperatures on High-k Stacked Dual Gate Junctionless MOSFET Performance: Analog and RF analysis
R Ghosh, RP Nelapati
Silicon 16 (2), 615-623, 2024
32024
Artificial Intelligence (AI)
R GHOSH
“Success is no accident. It is hard work, perseverance, learning, studying …, 0
3
Design and analysis of Z shaped InGa0. 5As0. 5/Si tunnel FET using non-equilibrium Green’s function model for hydrogen gas sensing application
R Ghosh, S Sarkhel, P Saha
Micro and Nanostructures 182, 207651, 2023
22023
MoS2 based dual gate MOSFET as ultra-sensitive SARs-CoV-2 biosensor for rapid screening of respiratory syndrome
R Ghosh, S Sarkhel, P Saha
IEEE Sensors Letters, 2023
22023
Investigating the linearity behavior of dual gate junction less MOSFET with high-K gate stack at cryogenic Temperatures
A Karmakar, R Ghosh, P Saha
2022 IEEE International Conference of Electron Devices Society Kolkata …, 2022
22022
Investigation of MoS2 Based Dual Gate MOSFET as a H2 Sensor Considering Catalytic Metal Gate Approach
A De, A Karmakar, R Ghosh, P Saha
IEEE VLSI DCS 2022, 4, 2022
22022
Sensitivity analysis of bi-metal stacked-gate-oxide hetero-juncture tunnel fet with Si0.6Ge0.4 source biosensor considering non-ideal factors
R Ghosh, RP Nelapati, P Saha, R Chinthaginjala, T Kim
Plos one 19 (6), e0301479, 2024
2024
Investigation of Analog/RF behaviour of Asymmetrical Gate Tunnel FET at Cryogenic temperatures
S Misra, C Bose, R Ghosh, P Saha
Silicon, 1-10, 2024
2024
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