| Reducing cache power with low-cost, multi-bit error-correcting codes C Wilkerson, AR Alameldeen, Z Chishti, W Wu, D Somasekhar, S Lu Proceedings of the 37th annual international symposium on Computer …, 2010 | 294 | 2010 |
| Energy-efficient cache design using variable-strength error-correcting codes AR Alameldeen, I Wagner, Z Chishti, W Wu, C Wilkerson, SL Lu ACM SIGARCH Computer Architecture News 39 (3), 461-472, 2011 | 224 | 2011 |
| Improving cache lifetime reliability at ultra-low voltages Z Chishti, AR Alameldeen, C Wilkerson, W Wu, SL Lu Proceedings of the 42nd Annual IEEE/ACM International Symposium on …, 2009 | 219 | 2009 |
| Optimizing NAND flash-based SSDs via retention relaxation RS Liu, CL Yang, W Wu Target 11 (10), 00, 2012 | 189 | 2012 |
| A systematic method for functional unit power estimation in microprocessors W Wu, L Jin, J Yang, P Liu, SXD Tan Proceedings of the 43rd annual Design Automation Conference, 554-557, 2006 | 98 | 2006 |
| Entropy loss in PUF-based key generation schemes: The repetition code pitfall P Koeberl, J Li, A Rajan, W Wu 2014 IEEE International Symposium on Hardware-Oriented Security and Trust …, 2014 | 87 | 2014 |
| Error detection and correction apparatus and method W Wu, SLL Lu, R Agarwal, H Stracovsky US Patent 9,043,674, 2015 | 74 | 2015 |
| Fast thermal simulation for architecture level dynamic thermal management P Liu, Z Qi, H Li, L Jin, W Wu, SXD Tan, J Yang ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 …, 2005 | 65 | 2005 |
| Adaptive cache design to enable reliable low-voltage operation AR Alameldeen, Z Chishti, C Wilkerson, W Wu, SL Lu IEEE Transactions on Computers 60 (1), 50-63, 2010 | 63 | 2010 |
| Method and apparatus for using cache memory in a system that supports a low power state CB Wilkerson, AR Alameldeen, ZA Chishti, D Somasekhar, W Wu, SL Lu US Patent 8,640,005, 2014 | 58 | 2014 |
| Efficient power modeling and software thermal sensing for runtime temperature monitoring W Wu, L Jin, J Yang, P Liu, SXD Tan ACM Transactions on Design Automation of Electronic Systems (TODAES) 12 (3 …, 2008 | 53 | 2008 |
| Dark bits to reduce physically unclonable function error rates K Gotze, G Iovino, D Johnston, P Koeberl, J Li, W Wu US Patent 9,992,031, 2018 | 48 | 2018 |
| Analysis on global exponential robust stability of reaction–diffusion neural networks with S-type distributed delays P Liu, F Yi, Q Guo, J Yang, W Wu Physica D: Nonlinear Phenomena 237 (4), 475-485, 2008 | 48 | 2008 |
| Increased redundancy in multi-device memory package to improve reliability W Wu, U Kang, H Alameer, R Agarwal, KE Criss, JB Halbert US Patent App. 15/814,336, 2018 | 42 | 2018 |
| Fast thermal simulation for runtime temperature tracking and management P Liu, H Li, L Jin, W Wu, SXD Tan, J Yang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006 | 41 | 2006 |
| Direct compare of information coded with error-correcting codes W Wu, D Somasekhar, SL Lu IEEE transactions on very large scale integration (VLSI) systems 20 (11 …, 2011 | 39 | 2011 |
| Efficient thermal simulation for run-time temperature tracking and management H Li, P Liu, Z Qi, L Jin, W Wu, SXD Tan, J Yang 2005 International Conference on Computer Design, 130-133, 2005 | 36 | 2005 |
| Low-power, resilient interconnection with orthogonal latin squares SE Lee, YS Yang, GS Choi, W Wu, R Iyer IEEE Design & Test of Computers 28 (2), 30-39, 2011 | 33 | 2011 |
| Efficient systems and methods for consuming and providing power C Wilkerson, M Zhang, W Wu US Patent App. 12/384,501, 2010 | 33 | 2010 |
| Performing multi-bit error correction on a cache line ZA Chishti, AR Alameldeen, C Wilkerson, W Wu, D Somasekhar, ... US Patent 8,245,111, 2012 | 22 | 2012 |
