| A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS P Meinerzhagen, O Andersson, B Mohammadi, Y Sherazi, A Burg, ... 2012 Proceedings of the ESSCIRC (ESSCIRC), 321-324, 2012 | 41 | 2012 |
| A 65 nm single stage 28 fJ/cycle 0.12 to 1.2 V level-shifter B Mohammadi, JN Rodrigues 2014 IEEE International Symposium on Circuits and Systems (ISCAS), 990-993, 2014 | 34 | 2014 |
| Ultra low voltage synthesizable memories: A trade-off discussion in 65 nm CMOS O Andersson, B Mohammadi, P Meinerzhagen, A Burg, JN Rodrigues IEEE Transactions on Circuits and Systems I: Regular Papers 63 (6), 806-817, 2016 | 29 | 2016 |
| A 128 kb 7T SRAM using a single-cycle boosting mechanism in 28-nm FD–SOI B Mohammadi, O Andersson, J Nguyen, L Ciampolini, A Cathelin, ... IEEE Transactions on Circuits and Systems I: Regular Papers 65 (4), 1257-1268, 2017 | 25 | 2017 |
| Dual-VT4kb sub-VTmemories with <1 pW/bit leakage in 65 nm CMOS O Andersson, B Mohammadi, P Meinerzhagen, A Burg, JN Rodrigues 2013 Proceedings of the ESSCIRC (ESSCIRC), 197-200, 2013 | 22 | 2013 |
| A 35 fJ/bit-access sub-VTmemory using a dual-bit area-optimized standard-cell in 65 nm CMOS O Andersson, B Mohammadi, P Meinerzhagen, JN Rodrigues ESSCIRC 2014-40th European Solid State Circuits Conference (ESSCIRC), 243-246, 2014 | 16 | 2014 |
| Stayin'Alive: An Interactive Augmented: Reality CPR Tutorial H Javaheri, A Gruenerbl, E Monger, M Gobbi, P Lukowicz Proceedings of the 2018 ACM International Joint Conference and 2018 …, 2018 | 9* | 2018 |
| Ultra low energy and area efficient charge pump with automatic clock controller in 65 nm CMOS B Mohammadi, J Rodrigues 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-4, 2015 | 9 | 2015 |
| A 128 kb single-bitline 8.4 fJ/bit 90MHz at 0.3 V 7T sense-amplifierless SRAM in 28 nm FD-SOI B Mohammadi, O Andersson, J Nguyen, L Ciampolini, A Cathelin, ... ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 429-432, 2016 | 8 | 2016 |
| Sizing of dual-VT gates for sub-VT circuits B Mohammadi, SMY Sherazi, JN Rodrigues 2012 IEEE Subthreshold Microelectronics Conference (SubVT), 1-3, 2012 | 8 | 2012 |
| SRAM architecture B Mohammadi, JN RODRIGUES US Patent 10,304,525, 2019 | 6 | 2019 |
| Ultra-low Power Design Approaches in Memories and Assist Techniques B Mohammadi | 3 | 2017 |
| A 0.28-0.8 V 320 fW D-latch for sub-VT memories in 65 nm CMOS B Mohammadi, O Andersson, P Meinerzhagen, Y Sherazi, A Burg, ... 2014 IEEE Faible Tension Faible Consommation, 1-4, 2014 | 3 | 2014 |
| An area efficient single-cycle xVDD sub-Vth on-chip boost scheme in 28 nm FD-SOI B Mohammadi, O Andersson, X Luo, M Nouripayam, JN Rodrigues 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), 229-232, 2016 | 1 | 2016 |
| Design of a Memory Compiler A Andersson, J Gustavsson, B Mohammadi, J Rodrigues Department of Electrical and Information Technology, Lund University, 2016 | 1 | 2016 |
| SRAM architecture B Mohammadi, JN RODRIGUES US Patent 10,811,084, 2020 | | 2020 |
| Application of Digital Resources in Distance Learning B Mohammadi Project and Conference Reports-CEE, LTH, 2013 | | 2013 |
| A 65-nm CMOS area optimized de-synchronization flow for sub-VTdesigns C Müller, S Malkowsky, O Andersson, B Mohammadi, J Sparsø, ... 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration …, 2013 | | 2013 |
| Clock tree design in sub-Vt circuits-Analysis on standard-and full-custom gates Y Liu, O Andersson, B Mohammadi, J Rodrigues | | 2013 |
| Two Flavors of 4kb Standard-Cell Based Subvt Memory in 65 nm CMOS O Andersson, P Meinerzhagen, B Mohammadi, SMY Sherazi, A Burg, ... Swedish System-On-Chip Conference (SSoCC), 2013, 2013 | | 2013 |
Joachim RodriguesAssociate Professor of Electrical Engineering, Lund University在 eit.lth.se 的电子邮件经过验证
