| High-speed electrical signaling: Overview and limitations M Horowitz, CKK Yang, S Sidiropoulos IEEE Micro 18 (1), 12-24, 1998 | 301 | 1998 |
| A 0.3-/spl mu/m CMOS 8-Gb/s 4-PAM serial link transceiver R Farjad-Rad, CKK Yang, MA Horowitz IEEE Journal of Solid-State Circuits 35 (5), 757-764, 2000 | 300 | 2000 |
| Fast frequency acquisition phase-frequency detectors for GSa/s phase-locked loops M Mansuri, D Liu, CKK Yang Proceedings of the 27th European Solid-State Circuits Conference, 333-336, 2001 | 272 | 2001 |
| A 0.5-/spl mu/m CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling CKK Yang, R Farjad-Rad, MA Horowitz IEEE Journal of Solid-State Circuits 33 (5), 713-722, 1998 | 263 | 1998 |
| A 0.4-/spl mu/m CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter R Farjad-Rad, CKK Yang, MA Horowitz, TH Lee IEEE Journal of Solid-State Circuits 34 (5), 580-585, 1999 | 202 | 1999 |
| A 27-mW 3.6-gb/s I/O transceiver KLJ Wong, H Hatamkhani, M Mansuri, CKK Yang IEEE Journal of Solid-State Circuits 39 (4), 602-612, 2004 | 198 | 2004 |
| A 0.8-/spl mu/m CMOS 2.5 Gb/s oversampling receiver and transmitter for serial links CKK Yang, MA Horowitz IEEE Journal of Solid-State Circuits 31 (12), 2015-2023, 1996 | 181 | 1996 |
| A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation M Mansuri, CKK Yang IEEE Journal of Solid-State Circuits 38 (11), 1804-1812, 2003 | 150 | 2003 |
| Offset compensation in comparators with minimum input-referred supply noise KLJ Wong, CKK Yang IEEE Journal of Solid-State Circuits 39 (5), 837-840, 2004 | 138 | 2004 |
| A serial-link transceiver based on 8-GSamples/s A/D and D/A converters in 0.25-/spl mu/m CMOS CKK Yang, V Stojanovic, S Modjtahedi, MA Horowitz, WF Ellersick IEEE Journal of Solid-State Circuits 36 (11), 1684-1692, 2001 | 119 | 2001 |
| Design of high-speed serial links in CMOS CKK Yang Stanford University, 1999 | 113 | 1999 |
| GAD: A 12-GS/s CMOS 4-bit A/D converter for an equalized multi-level link W Ellersick, CKK Yang, M Horowitz, W Dally 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No. 99CH36326 …, 1999 | 104 | 1999 |
| A 6.0-mW 10.0-Gb/s receiver with switched-capacitor summation DFE A Emami-Neyestanak, A Varzaghani, JF Bulzacchelli, A Rylyakov, ... IEEE Journal of Solid-State Circuits 42 (4), 889-896, 2007 | 103 | 2007 |
| Scalability and design-space analysis of a 1T-1MTJ memory cell for STT-RAMs R Dorrance, F Ren, Y Toriyama, AA Hafez, CKK Yang, D Markovic IEEE Transactions on Electron Devices 59 (4), 878-887, 2012 | 97 | 2012 |
| A 5-mW 6-Gb/s quarter-rate sampling receiver with a 2-tap DFE using soft decisions KLJ Wong, A Rylyakov, CKK Yang IEEE Journal of Solid-State Circuits 42 (4), 881-888, 2007 | 89 | 2007 |
| A CMOS 500 Mbps/pin synchronous point to point link interface S Sidiropoulos, CKK Yang, M Horowitz Proceedings of 1994 IEEE Symposium on VLSI Circuits, 43-44, 1994 | 85 | 1994 |
| Power optimized ADC-based serial link receiver EH Chen, R Yousry, CKK Yang IEEE Journal of Solid-State Circuits 47 (4), 938-951, 2012 | 84 | 2012 |
| Techniques for improving the accuracy of geometric-programming based analog circuit design optimization J Kim, J Lee, L Vandenberghe, CKK Yang IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004 …, 2004 | 81 | 2004 |
| A 14-bit, 10-Msamples/s D/A converter using multibit/spl Sigma//spl Delta/modulation K Falakshahi, CKK Yang, BA Wooley IEEE Journal of Solid-State Circuits 34 (5), 607-615, 1999 | 72 | 1999 |
| Delay-locked loops-an overview CKK Yang Phase-Locking in High-Performance Systems: From Devices to Architectures, 13-22, 2003 | 68 | 2003 |
Mark HorowitzProfessor of Electrical Engineering and Computer Science在 ee.stanford.edu 的电子邮件经过验证
