| Delay monitoring system with multiple generic monitors for wide voltage range operation J Kim, K Choi, Y Kim, W Kim, K Do, J Choi IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (1), 37-49, 2017 | 24 | 2017 |
| Early-life-failure detection using SAT-based ATPG M Sauer, YM Kim, J Seomun, HO Kim, KT Do, JY Choi, KS Kim, S Mitra, ... 2013 IEEE International Test Conference (ITC), 1-10, 2013 | 24 | 2013 |
| Statistical leakage estimation based on sequential addition of cell leakage currents W Kim, KT Do, YH Kim IEEE transactions on very large scale integration (VLSI) systems 18 (4), 602-615, 2009 | 22 | 2009 |
| Voltage monitor for generating delay codes J Seomun, S Insub, DO Kyungtae, C JungYun US Patent 9,984,732, 2018 | 13 | 2018 |
| Circuit having an active clock shielding structure and semiconductor intergrated circuit including the same BH Lee, J Choi, JH Jeon, KT Do US Patent 8,013,628, 2011 | 13 | 2011 |
| Adaptive delay monitoring for wide voltage-range operation J Kim, G Lee, K Choi, Y Kim, W Kim, K Do, J Choi 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 511-516, 2016 | 11 | 2016 |
| Clock domain crossing aware sequential clock gating J Liu, MS Hong, K Do, JY Choi, J Park, M Kumar, M Kumar, N Tripathi, ... 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2015 | 7 | 2015 |
| Detection of early-life failures in high-k metal-gate transistors and ultra low-k inter-metal dielectrics YM Kim, J Seomun, HO Kim, KT Do, JY Choi, KS Kim, M Sauer, B Becker, ... Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 1-4, 2013 | 6 | 2013 |
| Timing modeling of latch-controlled sub-systems KT Do, YH Kim, HS Son Integration 40 (2), 62-73, 2007 | 6 | 2007 |
| Thermal-aware body bias modulation for high performance mobile core C Oh, HO Kim, J Seomun, W Kim, J Jeon, KT Do, HS Won, KS Kim 2012 International SoC Design Conference (ISOCC), 147-150, 2012 | 5 | 2012 |
| Method of estimating a leakage current in a semiconductor device KT Do, J Choi, BH Lee, YH Kim, H Won, W Kim US Patent 8,156,460, 2012 | 3 | 2012 |
| System on chip and temperature control method thereof KIM Hyungock, W Kim, J Seomun, OH Chungki, J JaeHan, DO Kyungtae, ... US Patent 9,459,680, 2016 | 2 | 2016 |
| Design techniques to minimize the yield loss for general purpose ASIC/Soc devices JY Choi, BH Lee, KT Do, HO Kim, HS Won, KM Choi 2009 International SoC Design Conference (ISOCC), 45-48, 2009 | 2 | 2009 |
| Power modeling of synthesizable soft macros K Tae, YH Kim, YH Kim, JY Choi IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and …, 2004 | 1 | 2004 |
| Sequential analysis driven reset optimization to improve power, area and routability S Yechangunja, R Shekhar, M Kumar, N Tripathi, A Mittal, A Ranjan, J Liu, ... 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 551-554, 2016 | | 2016 |
| Methods of designing semiconductor devices and methods of modifying layouts of semiconductor devices KT Do, Y Lee, H Won, J Choi, JH Kim US Patent 8,621,399, 2013 | | 2013 |
| Comparison of characterization methods for statistical analysis of SoC designs W Kim, YH Kim, KT Do 2008 5th International Conference on Electrical Engineering/Electronics …, 2008 | | 2008 |
| Gate-Length Biasing for Low Leakage Design KT Do, BH Lee, JY Choi, HS Won, KM Choi 대한전자공학회 ISOCC, 319-321, 2007 | | 2007 |
| Monte Carlo Simulation for a SoC Design Using the Convergence Condition of Confidence Interval KT Do, YH Kim ITC-CSCC: International Technical Conference on Circuits Systems, Computers …, 2007 | | 2007 |
