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Stephen Cea
Stephen Cea
在 intel.com 的电子邮件经过验证
标题
引用次数
引用次数
年份
A 90-nm logic technology featuring strained-silicon
SE Thompson, M Armstrong, C Auth, M Alavi, M Buehler, R Chau, S Cea, ...
IEEE Transactions on electron devices 51 (11), 1790-1797, 2004
9472004
A logic nanotechnology featuring strained-silicon
SE Thompson, M Armstrong, C Auth, S Cea, R Chau, G Glass, T Hoffman, ...
IEEE Electron Device Letters 25 (4), 191-193, 2004
6982004
A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1/spl mu/m/sup 2/SRAM cell
S Thompson, N Anand, M Armstrong, C Auth, B Arcot, M Alavi, P Bai, ...
Digest. International Electron Devices Meeting,, 61-64, 2002
4562002
Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
N Lindert, SM Cea
US Patent 7,154,118, 2006
4092006
Silicon and silicon germanium nanowire structures
KJ Kuhn, S Kim, R Rios, SM Cea, MD Giles, A Cappellani, T Rakshit, ...
US Patent 8,753,942, 2014
3322014
Delaying forever: Uniaxial strained silicon transistors in a 90nm CMOS technology
K Mistry, M Armstrong, C Auth, S Cea, T Coan, T Ghani, T Hoffmann, ...
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004., 50-51, 2004
2132004
PMOS transistor strain optimization with raised junction regions
M Bohr, T Ghani, S Cea, K Mistry, C Auth, M Armstrong, K Zawadzki
US Patent App. 10/608,870, 2004
1922004
Two-dimensional condensation for uniaxially strained semiconductor fins
JT Kavalieros, NM Zelick, BY Jin, M Kuhn, SM Cea
US Patent 8,211,772, 2012
1912012
Through gate fin isolation
MT Bohr, SM Cea, BA Chappell
US Patent 11,037,923, 2021
1872021
Physics of hole transport in strained silicon MOSFET inversion layers
EX Wang, P Matagne, L Shifren, B Obradovic, R Kotlyar, S Cea, M Stettler, ...
IEEE Transactions on Electron Devices 53 (8), 1840-1851, 2006
1742006
CMOS nanowire structure
S Kim, KJ Kuhn, T Ghani, AS Murthy, A Cappellani, SM Cea, R Rios, ...
US Patent 9,224,810, 2015
1442015
Continuum based modeling of silicon integrated circuit processing: An object oriented approach
ME Law, SM Cea
Computational Materials Science 12 (4), 289-308, 1998
1381998
High mobility strained channels for fin-based transistors
SM Cea, AS Murthy, GA Glass, DB Aubertine, T Ghani, JT Kavalieros, ...
US Patent 8,847,281, 2014
1302014
Bandgap engineering of group IV materials for complementary n and p tunneling field effect transistors
R Kotlyar, UE Avci, S Cea, R Rios, TD Linton, KJ Kuhn, IA Young
Applied Physics Letters 102 (11), 2013
1202013
Gate-induced strain for MOS performance improvement
T Hoffman, SM Cea, MD Giles
US Patent 6,982,433, 2006
1122006
Wrap-around contacts for finfet and tri-gate devices
SM Cea, R Mehandru, L Shifren, K Kuhn
US Patent App. 12/646,651, 2011
1112011
Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
N Lindert, SM Cea
US Patent 7,326,634, 2008
992008
IEDM Tech. Dig.
S Thompson, N Anand, M Armstrong, C Auth, B Arcot, M Alavi, P Bai, ...
IEDM Tech. Dig, 61, 2002
992002
High performance Hi-K+ metal gate strain enhanced transistors on (110) silicon
P Packan, S Cea, H Deshpande, T Ghani, M Giles, O Golonzka, ...
2008 IEEE International Electron Devices Meeting, 1-4, 2008
872008
Silicon and silicon germanium nanowire structures
KJ Kuhn, S Kim, R Rios, SM Cea, MD Giles, A Cappellani, T Rakshit, ...
US Patent 9,129,829, 2015
792015
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