| Power grid structures and method of forming the same US Patent 11,251,124, 0 | 21* | |
| Power grid, IC and method for placing power grid H Biswas, KN Yang, CH Wang US Patent 10,672,709, 2020 | 13 | 2020 |
| Method of forming conductive grid of integrated circuit H Biswas, KN Yang, CH Wang US Patent 10,360,337, 2019 | 8 | 2019 |
| Inter-cell leakage-reducing method of generating layout diagram and system for same H Biswas, CH Wang, KN Yang, JH Lin US Patent 10,936,785, 2021 | 7 | 2021 |
| Semiconductor device including PG-aligned cells and method of generating layout of same H Biswas, CH Wang, KN Yang US Patent 10,878,163, 2020 | 7 | 2020 |
| Semiconductor device including PG-aligned cells and method of generating layout of same H Biswas, CH Wang, KN Yang US Patent 11,669,671, 2023 | 5 | 2023 |
| Semiconductor device including standard-cell-adapted power grid arrangement and method for generating layout diagram of same H Biswas, CH Wang, LIN Chin-Shen, KN Yang US Patent 10,943,045, 2021 | 4 | 2021 |
| Integrated circuit design method, system and computer program product LIN Chin-Shen, CH Wang, KN Yang, H Biswas US Patent 11,205,032, 2021 | 3 | 2021 |
| Power grid, IC and method for placing power grid H Biswas, KN Yang, CH Wang US Patent 11,068,638, 2021 | 3 | 2021 |
| Power grid, IC and method for placing power grid H Biswas, KN Yang, CH Wang US Patent 12,067,337, 2024 | 2 | 2024 |
| Method of fabricating semiconductor device including standard-cell-adapted power grid arrangement H Biswas, CH Wang, LIN Chin-Shen, KN Yang US Patent 11,347,922, 2022 | 2 | 2022 |
| Via sizing for IR drop reduction H Biswas, LIN Chin-Shen, KN Yang, CH Wang US Patent 10,867,916, 2020 | 2 | 2020 |
| Merged pillar structures and method of generating layout diagram of same H Biswas, CH Wang, KN Yang, YK Cheng US Patent 10,515,178, 2019 | 2 | 2019 |
| Method, system and computer program product for integrated circuit design LIN Chin-Shen, H Biswas, KN Yang, CH Wang US Patent App. 18/446,739, 2023 | 1 | 2023 |
| System and computer program product for integrated circuit design LIN Chin-Shen, H Biswas, KN Yang, CH Wang US Patent 11,775,725, 2023 | 1 | 2023 |
| Method of fabricating semiconductor device including standard-cell-adapted power grid arrangement H Biswas, CH Wang, LIN Chin-Shen, KN Yang US Patent 11,727,183, 2023 | 1 | 2023 |
| Integrated device and method of forming the same H Biswas, KN Yang, CH Wang, LEE Meng-Xiang US Patent 10,664,641, 2020 | 1 | 2020 |
| Integrated circuit and method of generating integrated circuit layout FY Chang, KN Yang, CH Wang, LC Lu, C Sheng-Fong, PH Huang, ... US Patent 10,515,944, 2019 | 1 | 2019 |
| METHOD OF GENERATING LAYOUT DIAGRAM INCLUDING MERGED PILLAR STRUCTURES H Biswas, C Wang, K Yang, Y Cheng US Patent App. 18/788,645, 2024 | | 2024 |
| Method of manufacturing a semiconductor device including PG-aligned cells H Biswas, CH Wang, KN Yang US Patent 12,112,117, 2024 | | 2024 |
