| Fixed-outline floorplanning: Block-position enumeration and a new method for calculating area costs S Chen, T Yoshimura Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 2008 | 71* | 2008 |
| Energy-efficient and high-throughput FPGA-based accelerator for Convolutional Neural Networks G Feng, Z Hu, S Chen, F Wu 2016 13th IEEE International Conference on Solid-State and Integrated …, 2016 | 68 | 2016 |
| Floorplanning and topology generation for application-specific network-on-chip B Yu, S Dong, S Chen, S Goto Design Automation Conference (ASP-DAC), 2010 15th Asia and South Pacific …, 2010 | 52 | 2010 |
| A resource-efficient pipelined architecture for real-time semi-global stereo matching Z Lu, J Wang, Z Li, S Chen, F Wu IEEE Transactions on Circuits and Systems for Video Technology 32 (2), 660-673, 2021 | 49 | 2021 |
| SaD-SLAM: A Visual SLAM Based on Semantic and Depth Information X Yuan, S Chen 2020 IEEE/RSJ International Conference on Intelligent Robots and Systems …, 2020 | 42 | 2020 |
| GoodFloorplan: Graph Convolutional Network and Reinforcement Learning-Based Floorplanning Q Xu, H Geng, S Chen, B Yuan, C Zhuo, Y Kang, X Wen IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021 | 31 | 2021 |
| Fast thermal analysis for fixed-outline 3D floorplanning Q Xu, S Chen Integration 59, 157-167, 2017 | 30 | 2017 |
| High throughput hardware architecture for accurate semi-global matching Y Li, Z Li, C Yang, W Zhong, S Chen Integration 65, 417-427, 2019 | 27 | 2019 |
| Application-specific network-on-chip synthesis with topology-aware floorplanning B Huang, S Chen, W Zhong, T Yoshimura 2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI), 1-6, 2012 | 26 | 2012 |
| Multi-layer floorplanning for stacked ICs: Configuration number and fixed-outline constraints S Chen, T Yoshimura INTEGRATION, the VLSI journal 43 (4), 378-388, 2010 | 26 | 2010 |
| Buffer planning as an integral part of floorplanning with consideration of routing congestion Y Ma, X Hong, S Dong, S Chen, CK Cheng, J Gu Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 2005 | 26 | 2005 |
| Clustered Fault Tolerance TSV Planning for 3-D Integrated Circuits Q Xu, S Chen, X Xu, B Yu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 25 | 2017 |
| Delay-driven layer assignment in global routing under multi-tier interconnect structure J Ao, S Dong, S Chen, S Goto Proceedings of the 2013 ACM International symposium on Physical Design, 101-107, 2013 | 25 | 2013 |
| Dynamic global buffer planning optimization based on detail block locating and congestion analysis Y Ma, X Hong, S Dong, S Chen, Y Cai, CK Cheng, J Gu Proceedings of the 40th annual Design Automation Conference, 806-811, 2003 | 25 | 2003 |
| Combining the ant system algorithm and simulated annealing for 3D/2D fixed-outline floorplanning Q Xu, S Chen, B Li Applied Soft Computing 40, 150-160, 2016 | 24 | 2016 |
| Floorplanning and topology synthesis for application-specific network-on-chips W Zhong, S Chen, B Huang, T Yoshimura, S Goto IEICE Transactions on Fundamentals of Electronics, Communications and …, 2013 | 23 | 2013 |
| Application-specific network-on-chip synthesis: Cluster generation and network component insertion W Zhong, B Yu, S Chen, T Yoshimura, S Dong, S Goto 2011 12th International Symposium on Quality Electronic Design, 1-6, 2011 | 22 | 2011 |
| Constraints generation for analog circuits layout Q Hao, S Chen, X Hong, Y Su, S Dong, Z Qu 2004 International Conference on Communications, Circuits and Systems (IEEE …, 2004 | 20 | 2004 |
| An integrated floorplanning with an efficient buffer planning algorithm Y Ma, X Hong, S Dong, S Chen, Y Cai, CK Cheng, J Gu Proceedings of the 2003 international symposium on Physical design, 136-142, 2003 | 19 | 2003 |
| A full layer parallel QC-LDPC decoder for WiMAX and Wi-Fi W Zhang, S Chen, X Bai, D Zhou 2015 IEEE 11th International Conference on ASIC (ASICON), 1-4, 2015 | 17 | 2015 |
Sheqin Dong 董社勤Associate Professor of Computer Science & Technology, Tsinghua University在 tsinghua.edu.cn 的电子邮件经过验证
