| Goal-oriented stimulus generation for analog circuits SN Ahmadyan, JA Kumar, S Vasudevan Proceedings of the 49th Annual Design Automation Conference, 1018-1023, 2012 | 23 | 2012 |
| Verifying dynamic power management schemes using statistical model checking JA Kumar, S Vasudevan 17th Asia and South Pacific Design Automation Conference, 579-584, 2012 | 15 | 2012 |
| Efficient statistical model checking of hardware circuits with multiple failure regions JA Kumar, SN Ahmadyan, S Vasudevan IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014 | 14 | 2014 |
| Runtime verification of nonlinear analog circuits using incremental time-augmented rrt algorithm SN Ahmadyan, JA Kumar, S Vasudevan 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 21-26, 2013 | 12 | 2013 |
| Automatic compositional reasoning for probabilistic model checking of hardware designs JA Kumar, S Vasudevan 2010 Seventh International Conference on the Quantitative Evaluation of …, 2010 | 11 | 2010 |
| Statistical guarantees of performance for RTL designs JA Kumar University of Illinois at Urbana-Champaign, 2012 | 8 | 2012 |
| Variation-conscious formal timing verification in RTL JA Kumar, S Vasudevan 2011 24th Internatioal Conference on VLSI Design, 58-63, 2011 | 8 | 2011 |
| Statistical guarantees of performance for MIMO designs JA Kumar, S Vasudevan 2010 IEEE/IFIP International Conference on Dependable Systems & Networks …, 2010 | 6 | 2010 |
| Formal probabilistic timing verification in RTL JA Kumar, S Vasudevan IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013 | 5 | 2013 |
| Scaling probabilistic timing verification of hardware using abstractions in design source code JA Kumar, L Liu, S Vasudevan 2011 Formal Methods in Computer-Aided Design (FMCAD), 196-205, 2011 | 5 | 2011 |
| Early prediction of NBTI effects using RTL source code analysis JA Kumar, KM Butler, H Kim, S Vasudevan Proceedings of the 49th Annual Design Automation Conference, 808-813, 2012 | 4 | 2012 |
| Sharpe: Variation-aware formal statistical timing analysis in rtl JA Kumar, S Vasudevan Coordinated Science Laboratory Report no. UILU-ENG-09-2218, CRHC-09-09, 2009 | 3 | 2009 |
| Formal performance analysis for faulty MIMO hardware JA Kumar, S Vasudevan IEEE transactions on very large scale integration (VLSI) systems 20 (10 …, 2011 | 1 | 2011 |
| A scalable approach for throughput estimation of timing speculation designs V Athavale, JA Kumar, S Vasudevan 2010 53rd IEEE International Midwest Symposium on Circuits and Systems, 1234 …, 2010 | 1 | 2010 |
| Formal timing verification in RTL in the presence of variations JA Kumar, S Vasudevan | | |
Shobha VasudevanProfessor of Computer Engineering, University of Illinois at Urbana-Champaign在 illinois.edu 的电子邮件经过验证
