| Subthreshold analog/RF performance enhancement of underlap DG FETs with high-k spacer for low power applications K Koley, A Dutta, B Syamal, SK Saha, CK Sarkar IEEE transactions on electron devices 60 (1), 63-69, 2012 | 69 | 2012 |
| Influence of Underlap on Gate Stack DG-MOSFET for analytical study of Analog/RF performance A Kundu, A Dasgupta, R Das, S Chakraborty, A Dutta, CK Sarkar Superlattices and Microstructures 94, 60-73, 2016 | 47 | 2016 |
| Analysis of High-Spacer Asymmetric Underlap DG-MOSFET for SOC Application K Koley, A Dutta, SK Saha, CK Sarkar IEEE Transactions on Electron Devices 62 (6), 1733-1738, 2015 | 45 | 2015 |
| Influence of channel length and high-K oxide thickness on subthreshold analog/RF performance of graded channel and gate stack DG-MOSFETs SK Swain, A Dutta, S Adak, SK Pati, CK Sarkar Microelectronics Reliability 61, 24-29, 2016 | 41 | 2016 |
| Impact of gate metal work-function engineering for enhancement of subthreshold analog/RF performance of underlap dual material gate DG-FET A Kundu, K Koley, A Dutta, CK Sarkar Microelectronics Reliability 54 (12), 2717-2722, 2014 | 29 | 2014 |
| Study of body and oxide thickness variation on analog and RF performance of underlap DG-MOSFETs SK Pati, K Koley, A Dutta, N Mohankumar, CK Sarkar Microelectronics Reliability 54 (6-7), 1137-1142, 2014 | 25 | 2014 |
| Effect of source/drain lateral straggle on distortion and intrinsic performance of asymmetric underlap DG-MOSFETs K Koley, A Dutta, SK Saha, CK Sarkar IEEE Journal of the Electron Devices Society 2 (6), 135-144, 2014 | 23 | 2014 |
| Analysis of high-k spacer on symmetric underlap DG-MOSFET with Gate Stack architecture R Das, S Chakraborty, A Dasgupta, A Dutta, A Kundu, CK Sarkar Superlattices and Microstructures 97, 386-396, 2016 | 17 | 2016 |
| Comparisons between dual and tri material gate on a 32 nm double gate MOSFET A Dasgupta, R Das, S Chakraborty, A Dutta, A Kundu, CK Sarkar Nano 11 (10), 1650117, 2016 | 15 | 2016 |
| Influence of channel length and high-K oxide thickness on subthreshold DC performance of graded channel and gate stack DG-MOSFETs S Adak, SK Swain, A Dutta, H Rahaman, CK Sarkar Nano 11 (09), 1650101, 2016 | 15 | 2016 |
| Analysis of Harmonic Distortion in UDG-MOSFETs A Dutta, K Koley, SK Saha, CK Sarkar IEEE Transactions on Electron Devices 61 (4), 998 - 1005, 2014 | 14 | 2014 |
| Impact of temperature on linearity and harmonic distortion characteristics of underlapped FinFET A Dutta, K Koley, SK Saha, CK Sarkar Microelectronics Reliability 61, 99-105, 2016 | 11 | 2016 |
| Physical Insights Into Electric Field Modulation in Dual-Spacer Asymmetric Underlap FinFET A Dutta, K Koley, SK Saha, CK Sarkar IEEE Transactions on Electron Devices 63 (8), 3019-3027, 2016 | 10 | 2016 |
| Analysis of Harmonic distortion in asymmetric underlap DG-MOSFET with high-< i> k</i> spacer A Dutta, K Koley, CK Sarkar Microelectronics Reliability 54 (6-7), 1125-1132, 2013 | 10 | 2013 |
| Effect of back oxide thickness of FDSOI on SRAM performance S Roy, S Mukherjee, A Dutta, CK Sarkar Superlattices and Microstructures 98, 316-324, 2016 | 9 | 2016 |
| Impact of underlap and mole-fraction on RF performance of strained-Si/Si1− xGex/strained-Si DG MOSFETs A Dutta, K Koley, CK Sarkar Superlattices and Microstructures 75, 634-646, 2014 | 9 | 2014 |
| Design and study of programmable ring oscillator using IDUDGMOSFET S Mukherjee, S Roy, K Koley, A Dutta, CK Sarkar Solid-State Electronics 117, 193-198, 2016 | 8 | 2016 |
| An analytical BTBT current model of symmetric/asymmetric 4T tunnel double gate FETs with ambipolar characteristic P Dutta, K Koley, A Dutta, CK Sarkar IEEE Transactions on Electron Devices 63 (7), 2700-2707, 2016 | 7 | 2016 |
| Influence on the analog/RF performance in graded channel Gate Stack DG-MOSFETs A Chattopadhyay, A Dutta, A Kundu, CK Sarkar 2016 3rd International Conference on Devices, Circuits and Systems (ICDCS …, 2016 | 7 | 2016 |
| Study on effect of back oxide thickness variation in FDSOI MOSFET on analogue circuit performance S Mukherjee, S Roy, A Dutta, CK Sarkar IET Circuits, Devices & Systems 10 (6), 497-503, 2016 | 6 | 2016 |
Samar SahaProspicient Devices在 ieee.org 的电子邮件经过验证
