| SOT-MRAM based analog in-memory computing for DNN inference J Doevenspeck, K Garello, B Verhoef, R Degraeve, S Van Beek, D Crotti, ... 2020 IEEE Symposium on VLSI Technology, 1-2, 2020 | 69 | 2020 |
| Unprecedented Thermoelectric Power Factor in SiGe Nanowires Field-Effect Transistors M Noroozi, G Jayakumar, K Zahmatkesh, J Lu, L Hultman, M Mensi, ... ECS Journal of Solid State Science and Technology 6 (9), Q114, 2017 | 45 | 2017 |
| Deterministic and field-free voltage-controlled MRAM for high performance and low power applications YC Wu, W Kim, K Garello, F Yasin, G Jayakumar, S Couet, R Carpenter, ... 2020 IEEE Symposium on VLSI Technology, 1-2, 2020 | 24 | 2020 |
| First demonstration of field-free perpendicular SOT-MRAM for ultrafast and high-density embedded memories K Cai, G Talmelli, K Fan, S Van Beek, V Kateel, M Gupta, MG Monteiro, ... 2022 International Electron Devices Meeting (IEDM), 36.2. 1-36.2. 4, 2022 | 22 | 2022 |
| Multi-pillar SOT-MRAM for Accurate Analog in-Memory DNN Inference J Doevenspeck, K Garello, S Rao, F Yasin, S Couet, G Jayakumar, ... 2021 Symposium on VLSI Technology, 1-2, 2021 | 21 | 2021 |
| BEOL compatible high retention perpendicular SOT-MRAM device for SRAM replacement and machine learning S Couet, S Rao, S Van Beek, VD Nguyen, K Garello, V Kateel, ... 2021 Symposium on VLSI Technology, 1-2, 2021 | 21 | 2021 |
| Silicon nanowires integrated with CMOS circuits for biosensing application G Jayakumar, A Asadollahi, PE Hellström, K Garidis, M Östling Solid-State Electronics 98, 26-31, 2014 | 21 | 2014 |
| Selective operations of multi-pillar SOT-MRAM for high density and low power embedded memories K Cai, S Van Beek, S Rao, K Fan, M Gupta, VD Nguyen, G Jayakumar, ... 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022 | 17 | 2022 |
| Wafer-scale HfO2 encapsulated silicon nanowire field effect transistor for efficient label-free DNA hybridization detection in dry environment G Jayakumar, M Legallais, PE Hellström, M Mouis, I Pignot-Paintrand, ... Nanotechnology 30 (18), 184002, 2019 | 15 | 2019 |
| Germanium on Insulator Fabrication for Monolithic 3-D Integration A Abedin, L Zurauskaite, A Asadollahi, K Garidis, G Jayakumar, BG Malm, ... IEEE Journal of the Electron Devices Society 6, 588-593, 2018 | 11 | 2018 |
| Fabrication and characterization of silicon nanowires using STL for biosensing applications G Jayakumar, K Garidis, PE Hellström, M Östling 2014 15th International Conference on Ultimate Integration on Silicon (ULIS …, 2014 | 9 | 2014 |
| Optimization of GOPS-Based Functionalization Process and Impact of Aptamer Grafting on the Si Nanonet FET Electrical Properties as First Steps towards Thrombin Electrical Detection M Vallejo-Perez, C Ternon, N Spinelli, F Morisot, C Theodorou, ... Nanomaterials 10 (9), 1842, 2020 | 8 | 2020 |
| Characterization of bonding surface and electrical insulation properties of inter layer dielectrics for 3D monolithic integration K Garidis, G Jayakumar, A Asadollahi, ED Litta, PE Hellström, M Östling EUROSOI-ULIS 2015: 2015 Joint International EUROSOI Workshop and …, 2015 | 8 | 2015 |
| MTJ degradation in SOT-MRAM by self-heating-induced diffusion S Van Beek, K Cai, S Rao, G Jayakumar, S Couet, N Jossart, A Chasin, ... 2022 IEEE International Reliability Physics Symposium (IRPS), 4A. 2-1-4A. 2-4, 2022 | 5 | 2022 |
| Pixel-based biosensor for enhanced control: silicon nanowires monolithically integrated with field-effect transistors in fully depleted silicon on insulator technology G Jayakumar, M Östling Nanotechnology 30 (22), 225502, 2019 | 5 | 2019 |
| Exploration of Scandium Doping in SbTe for Phase Change Memory Application M Barci, D Leonelli, X Zhou, X Wang, D Garbin, G Jayakumar, T Witters, ... IEEE Transactions on Electron Devices 69 (11), 6106-6112, 2022 | 4 | 2022 |
| A Comparison of Power Factor in N and P-Type SiGe Nanowires for Thermoelectric Applications M Noroozi, B Hamawandi, G Jayakumar, K Zahmatkesh, HH Radamson, ... Journal of Nanoscience and Nanotechnology 17 (3), 1622-1626, 2017 | 4 | 2017 |
| Electrical properties of sub-100 nm SiGe nanowires B Hamawandi, M Noroozi, G Jayakumar, A Ergül, K Zahmatkesh, ... Journal of Semiconductors 37 (10), 102001, 2016 | 4 | 2016 |
| Integration of Selective Epitaxial Growth of SiGe/Ge Layers in 14nm Node FinFETs G Wang, J Luo, C Qin, H Cui, J Liu, K Jia, J Li, T Yang, J Li, H Yin, C Zhao, ... ECS Transactions 75 (8), 273, 2016 | 4 | 2016 |
| Integration of Silicon Nanowires with CMOS PE Hellström, G Jayakumar, M Östling Beyond‐CMOS Nanodevices 1, 65-72, 2014 | 4 | 2014 |
Per-Erik HellströmKTH Royal Institute of Technology在 kth.se 的电子邮件经过验证
