| Tunnel field-effect transistors: Prospects and challenges UE Avci, DH Morris, IA Young IEEE Journal of the Electron Devices Society 3 (3), 88-95, 2015 | 499 | 2015 |
| Three-dimensional ferroelectric NOR-type memory DH Morris, UE Avci, IA Young US Patent 10,651,182, 2020 | 137 | 2020 |
| mLogic: Ultra-low voltage non-volatile logic circuits using STT-MTJ devices D Morris, D Bromberg, JG Zhu, L Pileggi Proceedings of the 49th Annual Design Automation Conference, 486-491, 2012 | 107 | 2012 |
| Design of Low Voltage Tunneling-FET Logic Circuits Considering Asymmetric Conduction Characteristics DH Morris, UE Avci, R Rios, IA Young IEEE, 2014 | 104 | 2014 |
| Energy efficiency comparison of nanowire heterojunction TFET and Si MOSFET at Lg=13nm, including P-TFET and variation considerations UE Avci, DH Morris, S Hasan, R Kotlyar, R Kim, R Rios, DE Nikonov, ... Electron Devices Meeting (IEDM), 2013 IEEE International, 33.4. 1-33.4. 4, 2013 | 91 | 2013 |
| Novel STT-MTJ device enabling all-metallic logic circuits DM Bromberg, DH Morris, L Pileggi, JG Zhu IEEE Transactions on Magnetics 48 (11), 3215-3218, 2012 | 79 | 2012 |
| Field Effect Transistors Having Ferroelectric or Antiferroelectric Gate Dielectric Structure S Kim, UE Avci, JM Howard, IA Young, DH Morris US Patent 11,735,652, 2023 | 52 | 2023 |
| Study of TFET non-ideality effects for determination of geometry and defect density requirements for sub-60mV/dec Ge TFET UE Avci, B Chu-Kung, A Agrawal, G Dewey, V Le, R Rios, DH Morris, ... 2015 IEEE International Electron Devices Meeting (IEDM), 34.5. 1-34.5. 4, 2015 | 51 | 2015 |
| Design and manufacturability tradeoffs in unidirectional and bidirectional standard cell layouts in 14 nm node K Vaidyanathan, SH Ng, D Morris, N Lafferty, L Liebmann, M Bender, ... Design for Manufacturability through Design-Process Integration VI 8327, 83270K, 2012 | 38 | 2012 |
| Real time stiffness display interface device for perception of virtual soft object A Song, D Morris, JE Colgate, MA Peshkin 2005 IEEE/RSJ International Conference on Intelligent Robots and Systems …, 2005 | 30 | 2005 |
| Configurable interconnect apparatus and method K Vaidyanathan, DH Morris, UE Avci, IA Young, T Karnik, H Liu US Patent 10,261,923, 2019 | 27* | 2019 |
| Tunneling field effect transistors: Device and circuit considerations for energy efficient logic opportunities IA Young, UE Avci, DH Morris 2015 IEEE International Electron Devices Meeting (IEDM), 22.1. 1-22.1. 4, 2015 | 27 | 2015 |
| System-Level Design and Integration of a Prototype AR/VR Hardware Featuring a Custom Low-Power DNN Accelerator Chip in 7nm Technology for Codec Avatars HE Sumbul, TF Wu, Y Li, SS Sarwar, W Koven, E Murphy-Trotzky, X Cai, ... 2022 IEEE Custom Integrated Circuits Conference (CICC), 01-08, 2022 | 26 | 2022 |
| Design of embedded memory and logic based on pattern constructs D Morris, K Vaidyanathan, N Lafferty, K Lai, L Liebmann, L Pileggi 2011 Symposium on VLSI Technology-Digest of Technical Papers, 104-105, 2011 | 26 | 2011 |
| Variation-tolerant dense TFET memory with low VMIN matching low-voltage TFET logic DH Morris, UE Avci, IA Young 2015 Symposium on VLSI Technology (VLSI Technology), T24-T25, 2015 | 25 | 2015 |
| Enabling application-specific integrated circuits on limited pattern constructs D Morris, V Rovner, L Pileggi, A Strojwas, K Vaidyanathan 2010 Symposium on VLSI Technology, 139-140, 2010 | 25 | 2010 |
| Naturally oxidized FeCo as a magnetic coupling layer for electrically isolated read/write paths in mLogic V Sokalski, DM Bromberg, D Morris, MT Moneck, E Yang, L Pileggi, ... IEEE Transactions on Magnetics 49 (7), 4351-4354, 2013 | 22 | 2013 |
| Frontiers in Electronics: Selected Papers from the Workshop on Frontiers in Electronics 2011 (WOFE-2011) DK SCHRODER, M SHATALOV, A LUNEV, X HU, O BILENKO, I GASKA, ... Selected topics in electronics and systems, In: Cristoloveanu S, Shur MS (Ed …, 2013 | 21* | 2013 |
| Ferroelectric based memory cell with non-volatile retention DH Morris, UE Avci, IA Young US Patent 10,573,385, 2020 | 20 | 2020 |
| Regular pattern arrays for memory and logic on a semiconductor substrate LT Pileggi, D Morris US Patent 8,198,655, 2012 | 20 | 2012 |
Ian A YoungIntel Corporation在 intel.com 的电子邮件经过验证
