| Analysis and optimization strategies toward reliable and high-speed 6T compute SRAM J Chen, W Zhao, Y Wang, Y Ha IEEE Transactions on Circuits and Systems I: Regular Papers 68 (4), 1520-1531, 2021 | 32 | 2021 |
| A reliable 8T SRAM for high-speed searching and logic-in-memory operations J Chen, W Zhao, Y Wang, Y Shu, W Jiang, Y Ha IEEE Transactions on Very Large Scale Integration (VLSI) Systems 30 (6), 769-780, 2022 | 21 | 2022 |
| Analysis and design of reconfigurable sense amplifier for compute SRAM with high-speed compute and normal read access J Chen, W Zhao, Y Wang, Y Ha IEEE Transactions on Circuits and Systems II: Express Briefs 68 (12), 3503-3507, 2021 | 13 | 2021 |
| Energy-efficient arbitrary precision multi-bit multiplication with bi-serial in/near memory computing Y Wang, J Chen, Y Pu, Y Ha 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020 | 5 | 2020 |
| A Reliable and High-Speed 6T Compute-SRAM Design With Dual-Split-VDD Assist and Bitline Leakage Compensation Y Wang, S Zhang, Y Li, J Chen, W Zhao, Y Ha IEEE Transactions on Very Large Scale Integration (VLSI) Systems 31 (5), 684-695, 2023 | 4 | 2023 |
| A 40nm 0.35 V 25MHz Half-Select Disturb-Free Bitinterleaving 10T SRAM With Data-Aware Write-Path Y Li, J Chen, Y Wang, Z Yin, H Chen, Y Ha 2023 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2023 | | 2023 |
| Low-power SRAM memory cell and application structure thereof Y Wang, Y Ha US Patent 11,100,979, 2021 | | 2021 |
Yajun HaProfessor, School of Information Science & Technology, ShanghaiTech University, China在 shanghaitech.edu.cn 的电子邮件经过验证
