| Reduced delay BCD adder AA Bayrakci, A Akkas 2007 IEEE International Conf. on Application-specific Systems, Architectures …, 2007 | 49 | 2007 |
| Fast Monte Carlo estimation of timing yield with importance sampling and transistor-level circuit simulation AA Bayrakci, A Demir, S Tasiran IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010 | 23 | 2010 |
| Hardware Trojan detection based on correlated path delays in defiance of variations with spatial correlations FN Esirci, AA Bayrakci Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017 | 17 | 2017 |
| Stochastic logical effort as a variation aware delay model to estimate timing yield AA Bayrakci Integration 48, 101-108, 2015 | 8 | 2015 |
| ELATE: Embedded low cost automatic test equipment for FPGA based testing of digital circuits AA Bayrakci 2017 10th International Conference on Electrical and Electronics Engineering …, 2017 | 6 | 2017 |
| Delay based hardware Trojan detection exploiting spatial correlations to suppress variations FN Esirci, AA Bayrakci Integration 91, 107-118, 2023 | 3 | 2023 |
| FPGA based low cost automatic test equipment for digital circuits AA Bayrakci Electrica 19 (1), 12-21, 2019 | 2 | 2019 |
| Fast Monte Carlo estimation of timing yield: Importance sampling with stochastic logical effort (ISLE) AA Bayrakci, A Demir, S Tasiran arXiv preprint arXiv:0805.2627, 2008 | 2 | 2008 |
| Acceleration of spatial correlation based hardware trojan detection using shared grids ratio FN Esirci, AA Bayrakci Mathematical Aspects of Computer and Information Sciences: 8th International …, 2020 | 1 | 2020 |
| On the accuracy of Monte Carlo yield estimators AA Bayrakci 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration …, 2013 | 1 | 2013 |
| BitEA: BitVertex Evolutionary Algorithm to Enhance Performance for Register Allocation GS Terci, E Abdulhalik, AA Bayrakci, B Boz IEEE Access, 2024 | | 2024 |
| FPGA Based Verification for the Difficulty of Delay Based Hardware Trojan Detection FN Esirci, H Mutlu, AA Bayrakci 2023 14th International Conference on Electrical and Electronics Engineering …, 2023 | | 2023 |
| Integer Point Enumeration in Multi-Dimensional Geometric Objects with FPGA Acceleration GS Terci, AA Bayrakci 2023 14th International Conference on Electrical and Electronics Engineering …, 2023 | | 2023 |
| PLODE: Precise Logic and Delay Simulator for Structural Verilog GN Erer, AA Bayrakci 2021 13th International Conference on Electrical and Electronics Engineering …, 2021 | | 2021 |
| Quantification of Power Based Hardware Trojan Detection Under Realistic Variations and Separation of Power Supplies M Kocabas, AA Bayrakci 2019 11th International Conference on Electrical and Electronics Engineering …, 2019 | | 2019 |
| Sayısal Devreler İçin FPGA Tabanlı Otomatik Test Cihazı (OTC) AA BAYRAKÇİ | | 2017 |
| Accelerated Accurate Timing Yield Estimation Based on Control Variates and Importance Sampling AA Bayrakci IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (8 …, 2016 | | 2016 |
| Fast and accurate statistical timing analysis of digital circuits for timing yield estimation based on transistor level simulations AA Bayrakçi Koç University, Turkey, 2010 | | 2010 |
| HCS12 EmumiS: Sanal HCS12 Geliştirme Aracı HCS12 EmumiS: Virtual HCS12 Development Tool H Ulutaş, AA Bayrakçi | | |
Fatma Nur EsirciComputer Engineering - Gebze Teknik Üniversitesi在 gtu.edu.tr 的电子邮件经过验证
Fatma Nur EsirciComputer Engineering - Gebze Teknik Üniversitesi在 gtu.edu.tr 的电子邮件经过验证
Alper DemirProfessor of Electrical Engineering, Koc University, Turkey在 ku.edu.tr 的电子邮件经过验证
Serdar TasiranS3, Amazon Web Services在 acm.org 的电子邮件经过验证