| Novel CMOS multi-bit counter for speed-power optimization in multiplier design A Saha, R Pal, AG Naik, D Pal AEU-International Journal of Electronics and Communications 95, 189-198, 2018 | 37 | 2018 |
| Low-power 6-GHz wave-pipelined 8b x 8b multiplier A Saha, D Pal, M Chandra Circuits, Devices & Systems, IET 7 (3), 124-140, 2013 | 27 | 2013 |
| DPL-based novel binary-to-ternary converter on CMOS technology A Saha, D Pal AEU-International Journal of Electronics and Communications 92, 69-73, 2018 | 24 | 2018 |
| Benchmarking of DPL-based 8b× 8b novel wave-pipelined multiplier A Saha, D Pal, M Chandra International Journal of Electronics Letters 5 (1), 115-128, 2016 | 20 | 2016 |
| DPL-based novel time equalized CMOS ternary-to-binary converter A Saha, D Pal International Journal of Electronics 107 (3), 431-443, 2019 | 19 | 2019 |
| DPL-based novel CMOS 1-trit ternary full-adder A Saha, RK Singh, P Gupta, D Pal International Journal of Electronics 108 (2), 218-236, 2021 | 15 | 2021 |
| Efficient ternary comparator on CMOS technology A Saha, ND Singh, D Pal Microelectronics Journal 109, 105005, 2021 | 14 | 2021 |
| Novel high speed MCML 8-bit by 8-bit multiplier A Saha, D Pal, M Chandra, MK Goswami 2011 International Conference on Devices and Communications (ICDeCom), 1-5, 2011 | 13 | 2011 |
| Systematic design strategy for DPL-based ternary logic circuit A Saha, ND Singh International Journal of Nanoparticles 12 (1-2), 3-16, 2020 | 10 | 2020 |
| Pair-wise Urdhava-Tiryagbhyam (UT) vedic ternary multiplier A Saha, RK Singh, D Pal Microelectronics Journal 119, 105318, 2022 | 9 | 2022 |
| LP-HS logic evaluation on TSMC 0.18 μm CMOS technology A Saha, S Kumar, D Das, M Chakraborty International Journal of High Speed Electronics and Systems 26 (04), 1740024, 2017 | 6 | 2017 |
| Novel self-pipelining approach for speed-power efficient reliable binary multiplication A Saha, R Pal, J Ghosh Micro and Nanosystems 12 (3), 149-158, 2020 | 4 | 2020 |
| Novel approach to design dpl-based ternary logic circuits ND Singh, RK Singh, R Raj, S Jyoti, A Saha 2018 IEEE Electron Devices Kolkata Conference (EDKCON), 631-635, 2018 | 4 | 2018 |
| Ternary Middle Value Decoder (T-MVD) on 90nm CMOS Technology M Gautam, P Rajhans, HK Verma, K Dulwani, R Chowdhury, P Sanyal, ... 2020 National Conference on Emerging Trends on Sustainable Technology and …, 2020 | 3 | 2020 |
| Novel 9: 1 Ternary Multiplexer on 32nm CMOS Technology R Pal, RK Singh, J Ghosh, A Saha 2021 Devices for Integrated Circuit (DevIC), 204-207, 2021 | 2 | 2021 |
| Novel Self-Pipelining Strategy for Efficient Multiplication R Pal, J Ghosh, A Saha 2019 Devices for Integrated Circuit (DevIC), 298-301, 2019 | 2 | 2019 |
| DPL-Based Novel 1-Trit Ternary Half-Subtractor R Raj, RK Singh, ND Singh, S Kumar, A Saha International Conference on Communication, Devices and Computing, 185-192, 2019 | 2 | 2019 |
| Fast Complete Ternary Addition with Novel 3: 1 T-Multiplexer A Saha, R Pal, T Kumari, RK Singh, S Chakraborty, J Ghosh Micro and Nanosystems 14 (4), 304-313, 2022 | 1 | 2022 |
| Efficient 3's Complement Circuit for Ternary-ALU. A Saha, S Dutta, S Dutta, OH Siddique, R Dey, AK Das Journal of Integrated Circuits & Systems 19 (1), 2024 | | 2024 |
| Speed-Power Efficient Novel CMOS Unary-to-Ternary Encoder A Saha, P Sanyal, DN Singh, A Bharti, D Pal IETE Journal of Research, 1-9, 2023 | | 2023 |
Prof. Dipankar PalProfessor, Dept. of EEE and E&I, BITS-Pilani, Goa在 goa.bits-pilani.ac.in 的电子邮件经过验证
