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Harijot Singh Bindra
标题
引用次数
引用次数
年份
A 1.2-V dynamic bias latch-type comparator in 65-nm CMOS with 0.4-mV input noise
HS Bindra, CE Lokin, D Schinkel, AJ Annema, B Nauta
IEEE journal of solid-state circuits 53 (7), 1902-1912, 2018
1882018
A 30fJ/comparison dynamic bias comparator
HS Bindra, CE Lokin, AJ Annema, B Nauta
ESSCIRC 2017-43rd IEEE European Solid State Circuits Conference, 71-74, 2017
532017
A 0.2-8 MS/s 10b flexible SAR ADC achieving 0.35-2.5 fJ/conv-step and using self-quenched dynamic bias comparator
HS Bindra, AJ Annema, SM Louwsma, B Nauta
2019 Symposium on VLSI Circuits, C74-C75, 2019
232019
A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2 V supply
HS Bindra, AJ Annema, G Wienk, B Nauta, SM Louwsma
2019 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2019
232019
A 174μVRMS Input Noise, 1 GS/s Comparator in 22nm FDSOI with a Dynamic-Bias Preamplifier Using Tail Charge Pump and Capacitive Neutralization Across the Latch
HS Bindra, J Ponte, B Nauta
2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022
182022
Energy efficient startup of crystal oscillators using stepwise charging
JB Lechevallier, HS Bindra, RAR van der Zee, B Nauta
IEEE journal of solid-state circuits 56 (8), 2427-2437, 2021
122021
An energy reduced sampling technique applied to a 10b 1MS/s SAR ADC
HS Bindra, AJ Annema, SM Louwsma, EJM van Tuijl, B Nauta
ESSCIRC 2017-43rd IEEE European Solid State Circuits Conference, 235-238, 2017
102017
Range pre-selection sampling technique to reduce input drive energy for SAR ADCs
HS Bindra, J Lechevallier, AJ Annema, S Louwsma, E van Tuijl, B Nauta
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), 217-220, 2017
82017
A 14-bit oversampled SAR ADC with mismatch error shaping and analog range compensation
Y Shen, H Li, HS Bindra, E Cantatore, P Harpe
IEEE Transactions on Circuits and Systems II: Express Briefs 70 (5), 1719-1723, 2023
72023
A 60 GHz pulsed coherent radar for online monitoring of the withering condition of leaves
NA Hoog, TE van den Berg, HS Bindra
Sensors and Actuators A: Physical 343, 113693, 2022
52022
Clock and data recovery module in 90nm for 10Gbps serial link with− 18dB channel attenuation
HS Bindra, S Chatterjee, K Saha, T Kukal
2013 IEEE International Symposium on Circuits and Systems (ISCAS), 2472-2475, 2013
32013
Reconstructing aliased frequency spectra by using multiple sample rates
M Huiskamp, MSO Alink, B Nauta, AJ Annema, HS Bindra
IEEE Transactions on Circuits and Systems I: Regular Papers 69 (3), 999-1012, 2021
22021
Low Energy Design Techniques for Data Converters
HS Bindra
12019
Reconstructing xxxxx
M Huiskamp, MSO Alink, B Nauta, AJ Annema, HS Bindra
IEEE transactions on circuits and systems I: regular papers, 2021
2021
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