| lp solve: a Mixed Integer Linear Program solver M Berkelaar, J Dirks | 906* | 1997 |
| Transistor sizing in MOS digital circuits with linear programming M Berkelaar, JAG Jess Proc. of the European Design Automation Conference,(Mierlo, The Netherlands …, 1990 | 226 | 1990 |
| LP solve: Opern Source (Mixed-Integer) Linear Programming System (2007) M Berkelaar http://lpsolve. sourceforge. net/5.5/, 2004 | 180* | 2004 |
| Statistical delay calculation, a linear time method M Berkelaar proc. TAU 97, 15-24, 1997 | 143 | 1997 |
| Gate sizing using a statistical delay model E Jacobs, MRCM Berkelaar Proceedings of the conference on Design, automation and test in Europe, 283-291, 2000 | 140 | 2000 |
| lpSolve: Interface to ‘Lp_solve’v. 5.5 to solve linear/integer programs M Berkelaar, K Eikland, P Notebaert R package version 5 (15), 1999, 2020 | 127 | 2020 |
| Computing the entire active area/power consumption versus delay tradeoff curve for gate sizing with a piecewise linear simulator MRCM Berkelaar, PHW Buurman, JAG Jess IEEE transactions on computer-aided design of integrated circuits and …, 1996 | 77 | 1996 |
| Technology mapping for standard-cell generators. MRCM Berkelaar, JAG Jess ICCAD, 470-473, 1988 | 70 | 1988 |
| lpSolve: interface to ‘Lp_solve’v. 5.5 to solve linear/integer programs. R package version 5.6. 13 M Berkelaar, J Dirks, K Eikland, P Notebaert, J Ebert, H Gourvest Vienna, Austria: R Foundation for Statistical Computing, 2015 | 37 | 2015 |
| Stochastic analysis of deep-submicrometer CMOS process for reliable circuits designs A Zjajo, Q Tang, M Berkelaar, JP de Gyvez, A Di Bucchianico, ... IEEE Transactions on Circuits and Systems I: Regular Papers 58 (1), 164-175, 2010 | 30 | 2010 |
| Efficient use of large don't cares in high-level and logic synthesis RA Bergamaschi, D Brand, L Stok, M Berkelaar, S Prakash Proceedings of IEEE International Conference on Computer Aided Design (ICCAD …, 1995 | 29 | 1995 |
| Using gate sizing to reduce glitch power E Jacobs, M Berkelaar Proceedings of the Prorisc/IEEE Workshop on Circuits, Systems and Signal …, 1996 | 28 | 1996 |
| RDE-based transistor-level gate simulation for statistical static timing analysis Q Tang, A Zjajo, M Berkelaar, N van der Meijs Proceedings of the 47th Design Automation Conference, 787-792, 2010 | 21 | 2010 |
| Area-power-delay trade-off in logic synthesis MRCM Berkelaar | 19 | 1992 |
| Efficient orthonormality testing for synthesis with pass-transistor selectors M Berkelaar, LPPP Van Ginneken Proceedings of IEEE International Conference on Computer Aided Design (ICCAD …, 1995 | 18 | 1995 |
| others. lpSolve: Interface to ‘Lp_solve’v. 5.5 to Solve Linear/Integer Programs; 2015 M Berkelaar URL http://CRAN. R-project. org/package= lpSolve. R package version 5 (11), 5.2, 0 | 17 | |
| Efficient and effective redundancy removal for million-gate circuits M Berkelaar, K van Eijk Proceedings 2002 Design, Automation and Test in Europe Conference and …, 2002 | 15 | 2002 |
| Improved state assignment for burst mode finite state machines J Rutten, MRCM Berkelaar Proceedings Third International Symposium on Advanced Research in …, 1997 | 15 | 1997 |
| others (2015)“lpSolve: Interface to Lpsolve v. 5.5 to solve linear–integer programs”. R package version 5.6. 13 M Berkelaar | 15 | |
| Static timing analysis Y Kukimoto, M Berkelaar, K Sakallah Logic Synthesis and Verification, 373-401, 2002 | 14 | 2002 |
