| Statistical timing analysis driven post-silicon-tunable clock-tree synthesis JL Tsai, L Zhang, CCP Chen ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 …, 2005 | 107 | 2005 |
| A yield improvement methodology using pre-and post-silicon statistical clock scheduling JL Tsai, DH Baik, CCP Chen, KK Saluja IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004 …, 2004 | 104 | 2004 |
| Sensitivity guided net weighting for placement driven synthesis TY Wang, JL Tsai, CCP Chen Proceedings of the 2004 international symposium on Physical design, 124-131, 2004 | 101 | 2004 |
| Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing JL Tsai, TH Chen, CCP Chen IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2004 | 94 | 2004 |
| Temperature-aware placement for SOCs JL Tsai, CCP Chen, G Chen, B Goplen, H Qian, Y Zhan, SM Kang, ... Proceedings of the IEEE 94 (8), 1502-1518, 2006 | 72 | 2006 |
| Thermal and power integrity based power/ground networks optimization TY Wang, JL Tsai, CCP Chen Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2004 | 37 | 2004 |
| Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time JL Tsai, TH Chen, CCP Chen Proceedings of the 2003 international symposium on Physical design, 166-173, 2003 | 19 | 2003 |
| Convergence-provable statistical timing analysis with level-sensitive latches and feedback loops L Zhang, J Tsai, W Chen, Y Hu, CCP Chen Proceedings of the 2006 Asia and South Pacific Design Automation Conference …, 2006 | 17 | 2006 |
| HiSIM: hierarchical interconnect-centric circuit simulator TH Chen, JL Tsai, CCP Chen, T Karnik IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004 …, 2004 | 14 | 2004 |
| Yield-driven, false-path-aware clock skew scheduling JL Tsai, DH Baik, CCP Chenm, KK Saluja IEEE design & test of computers 22 (3), 214-222, 2005 | 11 | 2005 |
| Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling JL Tsai, CCP Chen Proceedings of the 2005 Asia and South Pacific Design Automation Conference …, 2005 | 9 | 2005 |
| Clock tree synthesis for timing convergence and timing yield improvement in nanometer technologies JL Tsai The University of Wisconsin-Madison, 2005 | 9 | 2005 |
| Power-delivery networks optimization with thermal reliability integrity T Wang, J Tsai, C Chen ACM International Symposium on Physical Design (ISPD), 124-131, 2004 | 8 | 2004 |
| False path and clock scheduling based yield-aware gate sizing JL Tsai, DH Baik, CCP Chen, KK Saluja 18th International Conference on VLSI Design held jointly with 4th …, 2005 | 5 | 2005 |
| Simultaneous area minimization and decaps insertion for power delivery network using adjoint senstivity analysis with ieks method YM Lee, JL Tsai, CCP Chen Proc. of VLSI Design/CAD Symposium, 2003 | 4 | 2003 |
| Less restrictive knowledge connectivity condition for achieving consensus with unknown participants J Tsai, CC Chang IET Communications 6 (16), 2688-2694, 2012 | 1 | 2012 |
| Simultaneous area minimization and decaps insertion for power delivery network using adjoint sensitivity analysis with IEKS method PY Huang, YM Lee, JL Tsai, CCP Chen 2006 IEEE International Symposium on Circuits and Systems (ISCAS), 4 pp., 2006 | | 2006 |
| Self-Consistent Thermal-Aware Hierarchical Power/Ground Networks Optimization TY Wang, JL Tsai, CCP Chen | | 2003 |
| Statistical Clock Designs for Timing-Convergence and Timing-Yield Improvements in Deep Submicrometer Technologies JL Tsai, CCP Chen | | |
