| Strained Si: Opportunities and challenges in nanoscale MOSFET R Sharma, AK Rana 2015 IEEE 2nd International Conference on Recent Trends in Information …, 2015 | 15 | 2015 |
| Performance Evaluation of Negative Capacitance Junctionless FinFET under Extreme Length Scaling S Kaushal, AK Rana, R Sharma Silicon 13 (10), 3681-3690, 2021 | 14 | 2021 |
| Impact of High-k Spacer on Device Performance of Nanoscale Underlap Fully Depleted SOI MOSFET R Sharma, RS Rathore, AK Rana Journal of Circuits, Systems and Computers 27 (04), 1850063, 2018 | 14 | 2018 |
| Line edge roughness induced threshold voltage variability in nano-scale FinFETs RS Rathore, R Sharma, AK Rana Superlattices and Microstructures 103, 304-313, 2017 | 13 | 2017 |
| Threshold voltage variability induced by statistical parameters fluctuations in nanoscale bulk and SOI FinFETs RS Rathore, AK Rana, R Sharma 2017 4th International Conference on Signal Processing, Computing and …, 2017 | 8 | 2017 |
| Design and Investigation of Dual Dielectric Recessed-Gate AlGaN/GaN HEMT as Gas sensor Application A Raman, SP Chattopadhyay, R Ranjan, N Kumar, D Kakkar, R Sharma Transactions on Electrical and Electronic Materials 23 (6), 618-623, 2022 | 7 | 2022 |
| Scalability Projection of Underlap Fully Depleted Strained Ultra Thin Body Silicon-on-Insulator MOSFETs Using Quantum Potential Simulations R Sharma, AK Rana Journal of Nanoelectronics and Optoelectronics 11 (4), 472-476, 2016 | 5 | 2016 |
| Impact of Work Function Fluctuations on Threshold Voltage Variability in a Nanoscale FinFETs RS Rathore, R Sharma, AK Rana 2016 IEEE International Symposium on Nanoelectronic and Information Systems …, 2016 | 4 | 2016 |
| Analysis of Underlap Strained Silicon on Insulator MOSFET for Accurate and Compact Modeling R Sharma, AK Rana, S Kaushal, JB King, A Raman Silicon 14, 2793–2801, 2021 | 3 | 2021 |
| Probabilistic Behavioural Model Based on X-parameters AD Manjaly, R Sharma, J King 2020 IEEE Asia-Pacific Microwave Conference (APMC), 119-121, 2020 | 3 | 2020 |
| Nanoscale Static Random-Access-Memory Design Using Strained Underlap Ultra Thin Silicon on Insulator MOSFET for Improved Performance R Sharma, RS Rathore, AK Rana Journal of Nanoelectronics and Optoelectronics 12 (4), 359-364, 2017 | 3 | 2017 |
| Analytical modelling of threshold voltage for underlap Fully Depleted Silicon-On-Insulator MOSFET R Sharma, AK Rana International Journal of Electronics 104 (2), 286-296, 2017 | 2 | 2017 |
| Threshold voltage variability induced by spacer-and resist-defined patterning techniques in nanoscale FinFETs RS Rathore, R Sharma, AK Rana Journal of Micro/Nanolithography, MEMS, and MOEMS 16 (1), 013503, 2017 | 1 | 2017 |
| Power efficient multiplier using Vedic algorithm and self bias transistor technique K Choudhary, S Jadav, S Tayal, P Kaur, L Rai, R Sharma International Journal of Electronics, 1-15, 2022 | | 2022 |
Ashwani Kumar RanaAssociate Professor, NIT Hamirpur在 nith.ac.in 的电子邮件经过验证
Ashwani Kumar RanaAssociate Professor, NIT Hamirpur在 nith.ac.in 的电子邮件经过验证
Rituraj Singh RathoreHowards college, University of KwaZulu-Natal, Durban在 gweca.ac.in 的电子邮件经过验证