| A novel high-speed and energy efficient 10-transistor full adder design JF Lin, YT Hwang, MH Sheu, CC Ho IEEE Transactions on Circuits and Systems I: Regular Papers 54 (5), 1050-1059, 2007 | 306 | 2007 |
| Low-power pulse-triggered flip-flop design with conditional pulse-enhancement scheme YT Hwang, JF Lin, MH Sheu IEEE transactions on very large scale integration (VLSI) systems 20 (2), 361-366, 2011 | 129 | 2011 |
| Low-power pulse-triggered flip-flop design based on a signal feed-through JF Lin IEEE transactions on very large scale integration (vlsi) systems 22 (1), 181-185, 2013 | 93 | 2013 |
| Low-power 19-transistor true single-phase clocking flip-flop design based on logic structure reduction schemes JF Lin, MH Sheu, YT Hwang, CS Wong, MY Tsai IEEE transactions on very large scale integration (VLSI) systems 25 (11 …, 2017 | 69 | 2017 |
| Low voltage and low power divide-by-2/3 counter design using pass transistor logic circuit technique YT Hwang, JF Lin IEEE transactions on very large scale integration (vlsi) systems 20 (9 …, 2011 | 46 | 2011 |
| Low power 10-transistor full adder design based on degenerate pass transistor logic JF Lin, YT Hwang, MH Sheu 2012 IEEE International Symposium on Circuits and Systems (ISCAS), 496-499, 2012 | 32 | 2012 |
| Single‐ended structure sense‐amplifier‐based flip‐flop for low‐power systems JF Lin, YT Hwang, CS Wong, MH Sheu Electronics Letters 51 (1), 20-21, 2015 | 26 | 2015 |
| Low-power pulse-triggered flip–flop design using gated pull-up control scheme JF Lin Electronics letters 47 (24), 1313-1314, 2011 | 17 | 2011 |
| Low power multiplier designs based on improved column bypassing schemes YT Hwang, JF Lin, MH Sheu, CJ Sheu APCCAS 2006-2006 IEEE Asia Pacific Conference on Circuits and Systems, 594-597, 2006 | 14 | 2006 |
| Low power multipliers using enhenced row bypassing schemes YT Hwang, JF Lin, MH Sheu, CJ Sheu 2007 IEEE Workshop on Signal Processing Systems, 136-141, 2007 | 11 | 2007 |
| Novel low-complexity and low-power flip-flop design JF Lin, ZJ Hong, CM Tsai, BC Wu, SW Yu Electronics 9 (5), 783, 2020 | 10 | 2020 |
| An ultra-low-power true single-phase clocking flip-flop with improved hold time variation using logic structure reduction scheme MY Tsai, PY Kuo, JF Lin, MH Sheu 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2018 | 10 | 2018 |
| A novel cross-latch shift register scheme for low power applications PY Kuo, MH Sheu, CM Tsai, MY Tsai, JF Lin Applied Sciences 11 (1), 129, 2020 | 9 | 2020 |
| Semantic Lung Segmentation Using Convolutional Neural Networks PC Chang CS., Lin JF., Lee MC. Bildverarbeitung für die Medizin 2020, 2020 | 8* | 2020 |
| Low-Power and Low-Complextly Full Adder Design for Wireless Base Band Application M Sheu, Y Hwang 2006 International Conference on Communications, Circuits and Systems 4 …, 2006 | 7 | 2006 |
| Stable local bit-line 6 T SRAM architecture design for low-voltage operation and access enhancement MH Sheu, SMS Morsalin, CM Tsai, CJ Yang, SC Hsia, YH Hsueh, JF Lin, ... Electronics 10 (6), 685, 2021 | 6 | 2021 |
| A high speed and energy efficient full adder design using complementary & level restoring carry logic JF Lin, YT Hwang, MH Sheu, CC Ho 2006 IEEE International Symposium on Circuits and Systems (ISCAS), 4 pp., 2006 | 6 | 2006 |
| Novel low voltage and low power array multiplier design for IoT applications JF Lin, CY Chan, SW Yu Electronics 8 (12), 1429, 2019 | 5 | 2019 |
| A low power dual-mode pulse triggered flip-flop using pass transistor logic JF Lin, MH Sheu, PS Wang 2010 International Symposium on Next Generation Electronics, 203-206, 2010 | 4 | 2010 |
| Novel low complexity dual mode pulse generator designs MHS JF Lin, YT Hwang IEICE Trans. Fundamentals, 1812-1815, 2008 | 4* | 2008 |
