Delay monitoring system with multiple generic monitors for wide voltage range operation J Kim, K Choi, Y Kim, W Kim, K Do, J Choi IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (1), 37-49, 2017 | 24 | 2017 |
Statistical leakage estimation based on sequential addition of cell leakage currents W Kim, KT Do, YH Kim IEEE transactions on very large scale integration (VLSI) systems 18 (4), 602-615, 2009 | 22 | 2009 |
Modeling of FinFET self-heating effects in multiple FinFET technology generations with implication for transistor and product reliability HC Sagong, K Choi, J Kim, T Jeong, M Choe, H Shim, W Kim, J Park, ... 2018 IEEE Symposium on VLSI Technology, 121-122, 2018 | 20 | 2018 |
Timing yield slack for timing yield-constrained optimization and its application to statistical leakage minimization EJ Hwang, W Kim, YH Kim IEEE transactions on very large scale integration (VLSI) systems 21 (10 …, 2012 | 16 | 2012 |
Adaptive delay monitoring for wide voltage-range operation J Kim, G Lee, K Choi, Y Kim, W Kim, K Do, J Choi 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 511-516, 2016 | 11 | 2016 |
Method of generating standard cell library for dpl process and methods of producing a dpl mask and circuit pattern using the same W Kim, HO Kim, JY Choi, KS Kim, HS Won US Patent App. 13/616,507, 2013 | 10 | 2013 |
Improving the process variation tolerability of flip-flops for UDSM circuit design EJ Hwang, W Kim, YH Kim 2010 11th International Symposium on Quality Electronic Design (ISQED), 812-817, 2010 | 10 | 2010 |
Impact of process variation on timing characteristics of MTCMOS flip-flops for low-power mobile multimedia applications EJ Hwang, W Kim, YH Kim Proceedings of the 2009 12th International Symposium on Integrated Circuits …, 2009 | 10 | 2009 |
Efficient statistical timing analysis using deterministic cell delay models JH Kim, W Kim, YH Kim IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (11 …, 2014 | 8 | 2014 |
Evaluation of the state-of-the art statistical leakage estimation methods using the bsim4 transistor model J Kim, W Kim, YH Kim Proceedings of the 2009 12th International Symposium on Integrated Circuits …, 2009 | 7 | 2009 |
Timing criticality for timing yield optimization HS Park, W Kim, DJ Hyun, YH Kim IEICE transactions on fundamentals of electronics, communications and …, 2008 | 7 | 2008 |
Incremental statistical static timing analysis with gate timing yield emphasis JW Kim, W Kim, HS Park, YH Kim APCCAS 2008-2008 IEEE Asia Pacific Conference on Circuits and Systems, 1016-1019, 2008 | 6 | 2008 |
Thermal-aware body bias modulation for high performance mobile core C Oh, HO Kim, J Seomun, W Kim, J Jeon, KT Do, HS Won, KS Kim 2012 International SoC Design Conference (ISOCC), 147-150, 2012 | 5 | 2012 |
Method of incremental statistical static timing analysis based on timing yield J Kim, YH Kim, W Kim US Patent 8,046,725, 2011 | 4 | 2011 |
High Performance Level-Converting Flip-Flop with a Simple Pulse Generator and a Fast Latch HS Park, HB Che, W Kim, YH Kim ITC-CSCC: International Technical Conference on Circuits Systems, Computers …, 2008 | 4 | 2008 |
Method of estimating a leakage current in a semiconductor device KT Do, J Choi, BH Lee, YH Kim, H Won, W Kim US Patent 8,156,460, 2012 | 3 | 2012 |
System on chip and temperature control method thereof KIM Hyungock, W Kim, J Seomun, OH Chungki, J JaeHan, DO Kyungtae, ... US Patent 9,459,680, 2016 | 2 | 2016 |
Method of timing criticality calculation for statistical timing optimization of VLSI circuit HS Park, YH Kim, W Kim US Patent 8,046,724, 2011 | 2 | 2011 |
Event-based application modeling for analysis of asymmetric multicore-based mobile systems S Han, Y Yun, E Hwang, W Kim, YH Kim Journal of Systems Architecture 97, 477-490, 2019 | 1 | 2019 |
From WLR to product reliability and qualifications in the 3D transistor era S Pae, HC Sagong, C Liu, J Kim, M Jin, J Shim, Y Kim, J Jo, JK Park, ... 2015 IEEE International Integrated Reliability Workshop (IIRW), 68-68, 2015 | 1 | 2015 |