| An Ultra-Low Power Asynchronous-Logic In-Situ Self-Adaptive System for Wireless Sensor Networks T Lin, KS Chong, JS Chang, BH Gwee IEEE Journal of Solid-State Circuits 48 (2), 573-586, 2012 | 56 | 2012 |
| Fine-grained power gating for leakage and short-circuit power reduction by using asynchronous-logic T Lin, KS Chong, BH Gwee, JS Chang 2009 IEEE International Symposium on Circuits and Systems (ISCAS), 3162-3165, 2009 | 46 | 2009 |
| Hybrid -Means Clustering and Support Vector Machine Method for via and Metal Line Detections in Delayered IC Images D Cheng, Y Shi, T Lin, BH Gwee, KA Toh IEEE Transactions on Circuits and Systems II: Express Briefs 65 (12), 1849-1853, 2018 | 36 | 2018 |
| Deep learning for automatic IC image analysis X Hong, D Cheng, Y Shi, T Lin, BH Gwee 2018 IEEE 23rd International Conference on Digital Signal Processing (DSP), 1-5, 2018 | 34 | 2018 |
| Deep learning-based image analysis framework for hardware assurance of digital integrated circuits T Lin, Y Shi, N Shu, D Cheng, X Hong, J Song, BH Gwee Microelectronics Reliability 123, 114196, 2021 | 31 | 2021 |
| Sense amplifier half-buffer (SAHB) a low-power high-performance asynchronous logic QDI cell template KS Chong, WG Ho, T Lin, BH Gwee, JS Chang IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (2), 402-415, 2016 | 24 | 2016 |
| A hierarchical multiclassifier system for automated analysis of delayered IC images D Cheng, Y Shi, BH Gwee, KA Toh, T Lin IEEE Intelligent Systems 34 (2), 36-43, 2018 | 22 | 2018 |
| Global template projection and matching method for training-free analysis of delayered IC images D Cheng, Y Shi, T Lin, BH Gwee, KA Toh 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019 | 17 | 2019 |
| Analytical delay variation modeling for evaluating sub-threshold synchronous/asynchronous designs T Lin, KS Chong, BH Gwee, JS Chang, ZX Qiu Proceedings of the 8th IEEE International NEWCAS Conference 2010, 69-72, 2010 | 17 | 2010 |
| Total Ionizing Dose (TID) effects on finger transistors in a 65nm CMOS process J Jiang, W Shu, KS Chong, T Lin, NKZ Lwin, JS Chang, J Liu 2016 IEEE international symposium on circuits and systems (ISCAS), 5-8, 2016 | 15 | 2016 |
| Asic circuit netlist recognition using graph neural network X Hong, T Lin, Y Shi, BH Gwee 2021 IEEE International Symposium on the Physical and Failure Analysis of …, 2021 | 11 | 2021 |
| Experimental investigation into radiation-hardening-by-design (RHBD) flip-flop designs in a 65nm CMOS process T Lin, KS Chong, W Shu, NKZ Lwin, J Jiang, JS Chang 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 966-969, 2016 | 11 | 2016 |
| Radiation-hardened library cell template and its total ionizing dose (TID) delay characterization in 65nm CMOS process JS Chang, KS Chong, W Shu, T Lin, J Jiang, NKZ Lwin, Y Kang 2014 IEEE 57th International Midwest Symposium on Circuits and Systems …, 2014 | 11 | 2014 |
| Fully-additive printed electronics on flexible substrates: A fully-additive RFID tag T Ge, JS Chang, T Lin, Z Lei, LG Soon 2014 IEEE 57th International Midwest Symposium on Circuits and Systems …, 2014 | 9 | 2014 |
| Delayered IC image analysis with template‐based Tanimoto Convolution and Morphological Decision D Cheng, Y Shi, T Lin, BH Gwee, KA Toh IET Circuits, Devices & Systems 16 (2), 169-177, 2022 | 7 | 2022 |
| Joint anomaly detection and inpainting for microscopy images via deep self-supervised learning L Huang, D Cheng, X Yang, T Lin, Y Shi, K Yang, BH Gwee, B Wen 2021 IEEE International Conference on Image Processing (ICIP), 3497-3501, 2021 | 5 | 2021 |
| A robust asynchronous approach for realizing ultra-low power digital Self-Adaptive VDD Scaling system T Lin, KS Chong, JS Chang, BH Gwee, W Shu 2012 IEEE Subthreshold Microelectronics Conference (SubVT), 1-3, 2012 | 5 | 2012 |
| A dual-core 8051 microcontroller system based on synchronous-logic and asynchronous-logic KL Chang, T Lin, WG Ho, KS Chong, BH Gwee, JS Chang 2013 IEEE International Symposium on Circuits and Systems (ISCAS), 3022-3025, 2013 | 4 | 2013 |
| Energy-delay efficient asynchronous-logic 16× 16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic WG Ho, KS Chong, T Lin, BH Gwee, JS Chang 2012 IEEE International Symposium on Circuits and Systems (ISCAS), 492-495, 2012 | 4 | 2012 |
| Patch-based adversarial training for error-aware circuit annotation of delayered ic images YY Tee, X Hong, D Cheng, CS Chee, Y Shi, T Lin, BH Gwee IEEE Transactions on Circuits and Systems II: Express Briefs 70 (9), 3694-3698, 2023 | 3 | 2023 |
