| Multi-chip package structure having chip interconnection bridge which provides power connections between chip and package substrate J Rubin, LA Clevenger, CL Arvin US Patent 10,535,608, 2020 | 44 | 2020 |
| Multi-chip package structures with discrete redistribution layers JM Rubin, KK Sikka, SL Wright, LA Clevenger US Patent 11,164,817, 2021 | 38 | 2021 |
| Interlayer via contacts for monolithic three-dimensional semiconductor integrated circuit devices JM Rubin, N Loubet, TB Hook US Patent 10,748,901, 2020 | 37 | 2020 |
| Self-aligned air gap spacer for nanosheet CMOS devices S Mochizuki, A Reznicek, JM Rubin, J Wang US Patent 10,243,043, 2019 | 37 | 2019 |
| Self-aligned air gap spacer for nanosheet CMOS devices S Mochizuki, A Reznicek, JM Rubin, J Wang US Patent 9,954,058, 2018 | 36 | 2018 |
| Direct bonded heterogeneous integration packaging structures KK Sikka, JA Casey, J Rubin, A Kumar, D Gupta, CL Arvin, ... US Patent 10,580,738, 2020 | 31 | 2020 |
| Gate metal patterning for tight pitch applications S Mochizuki, A Reznicek, JM Rubin, J Wang US Patent 10,103,065, 2018 | 28 | 2018 |
| Back-side memory element with local memory select transistor A Kumar, JM Rubin US Patent 10,446,606, 2019 | 22 | 2019 |
| Back-side memory element with local memory select transistor A Kumar, JM Rubin US Patent 11,101,318, 2021 | 18 | 2021 |
| Multi-chip package structures having embedded chip interconnect bridges and fan-out redistribution layers JM Rubin, SL Wright, LA Clevenger US Patent 11,094,637, 2021 | 18 | 2021 |
| Reducing gate resistance in stacked vertical transport field effect transistors H Wu, C Zhang, K Cheng, T Yamashita, JM Rubin US Patent 11,069,679, 2021 | 17 | 2021 |
| Metallized junction FinFET structures BB Doris, P Kerber, A Reznicek, JM Rubin US Patent 9,627,410, 2017 | 15 | 2017 |
| Gate metal patterning to avoid gate stack attack due to excessive wet etching J Wang, A Reznicek, S Mochizuki, J Rubin US Patent 10,573,521, 2020 | 14 | 2020 |
| Interlayer via VS Basker, LA Clevenger, TB Hook, JM Rubin, T Yamashita US Patent 9,711,501, 2017 | 14 | 2017 |
| Contact formation for stacked vertical transport field-effect transistors H Wu, T Yamashita, C Zhang, JM Rubin US Patent 11,164,791, 2021 | 13 | 2021 |
| Tensile strained high percentage silicon germanium alloy FinFETs BB Doris, P Hashemi, A Reznicek, JM Rubin, RM Schulz US Patent 9,812,571, 2017 | 13 | 2017 |
| Power distribution networks for monolithic three-dimensional semiconductor integrated circuit devices JM Rubin, TB Hook US Patent 10,607,938, 2020 | 12 | 2020 |
| Three-dimensional monolithic vertical field effect transistor logic gates T Hook, A Rahman, J Rubin, C Zhang US Patent 10,217,674, 2019 | 12 | 2019 |
| A low-voltage torsion nanorelay J Rubin, R Sundararaman, M Kim, S Tiwari IEEE electron device letters 32 (3), 414-416, 2011 | 12 | 2011 |
| Nanosheet structure with isolated gate A Reznicek, X Miao, J Rubin US Patent 10,679,890, 2020 | 11 | 2020 |
