RT-level ITC'99 benchmarks and first ATPG results F Corno, MS Reorda, G Squillero IEEE Design & Test of computers 17 (3), 44-53, 2000 | 702 | 2000 |
Microprocessor software-based self-testing M Psarakis, D Gizopoulos, E Sanchez, MS Reorda IEEE Design & Test of Computers 27 (3), 4-19, 2010 | 331 | 2010 |
Soft-error detection using control flow assertions O Goloubeva, M Rebaudengo, MS Reorda, M Violante Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI …, 2003 | 330 | 2003 |
On the optimal design of triple modular redundancy logic for SRAM-based FPGAs FL Kastensmidt, L Sterpone, L Carro, MS Reorda Design, Automation and Test in Europe, 1290-1295, 2005 | 317 | 2005 |
Soft-error detection through software fault-tolerance techniques M Rebaudengo, MS Reorda, M Torchiano, M Violante Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance …, 1999 | 232 | 1999 |
Software-implemented hardware fault tolerance O Goloubeva, M Rebaudengo, MS Reorda, M Violante Springer Science & Business Media, 2006 | 208 | 2006 |
Automatic test program generation: a case study F Corno, E Sánchez, MS Reorda, G Squillero IEEE Design & Test of Computers 21 (2), 102-109, 2004 | 187 | 2004 |
GATTO: A genetic algorithm for automatic test pattern generation for large synchronous sequential circuits F Corno, P Prinetto, M Rebaudengo, MS Reorda IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1996 | 183 | 1996 |
Identification and classification of single-event upsets in the configuration memory of SRAM-based FPGAs M Ceschia, M Violante, MS Reorda, A Paccagnella, P Bernardi, ... IEEE Transactions on Nuclear Science 50 (6), 2088-2094, 2003 | 173 | 2003 |
Low power BIST via non-linear hybrid cellular automata F Corno, M Rebaudengo, MS Reorda, G Squillero, M Violante Proceedings 18th IEEE VLSI Test Symposium, 29-34, 2000 | 164 | 2000 |
Experimentally evaluating an automatic approach for generating safety-critical software with respect to transient errors P Cheynet, B Nicolescu, R Velazco, M Rebaudengo, MS Reorda, ... IEEE Transactions on Nuclear Science 47 (6), 2231-2236, 2000 | 152 | 2000 |
A source-to-source compiler for generating dependable software M Rebaudengo, MS Reorda, M Violante, M Torchiano Proceedings First IEEE International Workshop on Source Code Analysis and …, 2001 | 141 | 2001 |
A test pattern generation methodology for low power consumption E Corno, P Prinetto, M Rebaudengo, MS Reorda Proceedings. 16th IEEE VLSI Test Symposium (Cat. No. 98TB100231), 453-457, 1998 | 141 | 1998 |
Fully automatic test program generation for microprocessor cores F Corno, G Cumani, MS Reorda, G Squillero 2003 Design, Automation and Test in Europe Conference and Exhibition, 1006-1011, 2003 | 133 | 2003 |
A diagnostic test pattern generation algorithm P Camurati, D Medina, P Prinetto, MS Reorda Proceedings. International Test Conference 1990, 52-58, 1990 | 133 | 1990 |
Evaluating the effects of SEUs affecting the configuration memory of an SRAM-based FPGA M Bellato, P Bernardi, D Bortolato, A Candelori, M Ceschia, ... Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2004 | 132 | 2004 |
An automatic test pattern generator for large sequential circuits based on genetic algorithms P Prinetto, M Rebaudengo, MS Reorda Proceedings., International Test Conference, 240-249, 1995 | 129 | 1995 |
An FPGA-based approach for speeding-up fault injection campaigns on safety-critical circuits P Civera, L Macchiarulo, M Rebaudengo, MS Reorda, M Violante Journal of Electronic Testing 18, 261-271, 2002 | 127 | 2002 |
New techniques for speeding-up fault-injection campaigns L Berrojo, I González, F Corno, MS Reorda, G Squillero, L Entrena, ... Proceedings 2002 Design, Automation and Test in Europe Conference and …, 2002 | 121 | 2002 |
Exploiting circuit emulation for fast hardness evaluation P Civera, L Macchiarulo, M Rebaudengo, MS Reorda, M Violante IEEE Transactions on Nuclear Science 48 (6), 2210-2216, 2001 | 121 | 2001 |