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Arnav Goel
Arnav Goel
University of Southern California; Birla Institute of Technology & Science, Pilani;
在 usc.edu 的电子邮件经过验证
标题
引用次数
引用次数
年份
Hardware solution for real-time face recognition
G Mahale, H Mahale, A Goel, SK Nandy, S Bhattacharya, R Narayan
2015 28th International Conference on VLSI Design, 81-86, 2015
172015
Inter-node buffer-based streaming for reconfigurable processor-as-a-service (RPaaS)
R Sivaramakrishnan, S Jairath, EA Burhan, MK Shah, R Prabhakar, ...
US Patent 11,182,221, 2021
82021
Intra-node buffer-based streaming for reconfigurable processor-as-a-service (RPaaS)
R Sivaramakrishnan, S Jairath, EA Burhan, MK Shah, R Prabhakar, ...
US Patent 11,182,264, 2021
62021
Time-multiplexed use of reconfigurable hardware
A Misra, G Arnav, Q Zheng, R Shenbagam, R Kumar
US Patent 11,782,760, 2023
42023
Inter-node execution of configuration files on reconfigurable processors using smart network interface controller (smartnic) buffers
R Sivaramakrishnan, S Jairath, EA Burhan, MK Shah, R Prabhakar, ...
US Patent 11,625,284, 2023
32023
Runtime virtualization of reconfigurable data flow resources
R Kumar, CA Turlik, G Arnav, Q Zheng, R Shenbagam, A Misra, ...
US Patent 11,809,908, 2023
22023
Elevated Isolation of Reconfigurable Data Flow Resources in Cloud Computing
R Chatterjee, R Kumar, R Shenbagam, M Wilson, CA Turlik, G Arnav, ...
US Patent App. 18/084,013, 2023
22023
System of Heterogeneous Reconfigurable Processors for the Data-Parallel Execution of Applications
G Dykema, M Wilson, G Feng, K Zhou, T Sun, LEE Taylor, KH Leung, ...
US Patent App. 17/941,947, 2023
12023
Inter-processor execution of configuration files on reconfigurable processors using smart network interface controller (SmartNIC) buffers
R Sivaramakrishnan, S Jairath, EA Burhan, MK Shah, R Prabhakar, ...
US Patent 11,625,283, 2023
12023
Runtime execution of configuration files on reconfigurable processors with varying configuration granularity
R Sivaramakrishnan, S Jairath, EA Burhan, MK Shah, R Prabhakar, ...
US Patent 11,609,798, 2023
12023
Debugging framework for a reconfigurable data processor
G Arnav, Q Zheng, G Feng, C Yang, J Luo
US Patent App. 18/244,677, 2024
2024
Intelligent graph execution and orchestration engine for a reconfigurable data processor
G Arnav, R Kumar, A Sabnis, Q Zheng, N Sanghvi
US Patent App. 18/243,994, 2024
2024
Auto-Discovery Module for the Discovery of Reconfigurable Processors in a Pool of Heterogeneous Reconfigurable Processors
G Dykema, M Wilson, G Feng, K Zhou, T Sun, LEE Taylor, KH Leung, ...
US Patent App. 18/635,114, 2024
2024
Method and apparatus for data access in a heterogeneous processing system with multiple processors using memory extension operation
G Arnav, N Sanghvi, BAI Jiayu, Q Zheng, R Kumar
US Patent App. 18/099,021, 2024
2024
Method and apparatus for selecting data access method in a heterogeneous processing system with multiple processors
G Arnav, N Sanghvi, BAI Jiayu, Q Zheng, R Kumar
US Patent App. 18/099,032, 2024
2024
Method and apparatus for data transfer between accessible memories of multiple processors in a heterogeneous processing system using two memory to memory transfer operations
G Arnav, N Sanghvi, BAI Jiayu, Q Zheng, R Kumar
US Patent App. 18/099,006, 2024
2024
Method and apparatus for data transfer between accessible memories of multiple processors in a heterogeneous processing system using one memory to memory transfer operation
G Arnav, N Sanghvi, BAI Jiayu, Q Zheng, R Kumar
US Patent App. 18/099,014, 2024
2024
Data transfer in dataflow computing systems using an intelligent dynamic transfer engine
Q Zheng, G Arnav, CA Turlik, G Feng, JE Polzin, F Cheng, R Kumar, ...
US Patent App. 18/614,639, 2024
2024
System for executing an application on heterogeneous reconfigurable processors
G Dykema, M Wilson, G Feng, K Zhou, T Sun, LEE Taylor, KH Leung, ...
US Patent 11,983,141, 2024
2024
Fast receive re-convergence of multi-pod multi-destination traffic in response to local disruptions
H Narasimhan, S Narayanaswamy, BM Mammen, B Muthuvarathan, ...
US Patent 11,936,559, 2024
2024
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