On-the-fly composition of FPGA-based SQL query accelerators using a partially reconfigurable module library C Dennl, D Ziener, J Teich 2012 IEEE 20th International Symposium on Field-Programmable Custom …, 2012 | 105 | 2012 |
Power signature watermarking of IP cores for FPGAs D Ziener, J Teich Journal of Signal Processing Systems 51, 123-136, 2008 | 93 | 2008 |
FPGAs for software programmers D Koch, F Hannig, D Ziener Springer, 2016 | 92 | 2016 |
Acceleration of SQL restrictions and aggregations through FPGA-based dynamic partial reconfiguration C Dennl, D Ziener, J Teich 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom …, 2013 | 71 | 2013 |
Identifying FPGA IP-cores based on lookup table content analysis D Ziener, S Aßmus, J Teich 2006 international conference on field programmable logic and applications, 1-6, 2006 | 71 | 2006 |
Netlist-level IP protection by watermarking for LUT-based FPGAs M Schmid, D Ziener, J Teich 2008 International Conference on Field-Programmable Technology, 209-216, 2008 | 69 | 2008 |
FPGA-based dynamically reconfigurable SQL query processing D Ziener, F Bauer, A Becher, C Dennl, K Meyer-Wegener, U Schürfeld, ... ACM Transactions on Reconfigurable Technology and Systems (TRETS) 9 (4), 1-24, 2016 | 63 | 2016 |
Partial reconfiguration on FPGAs in practice—Tools and applications D Koch, J Torresen, C Beckhoff, D Ziener, C Dennl, V Breuer, J Teich, ... ARCS 2012, 1-12, 2012 | 57 | 2012 |
Energy-aware SQL query acceleration through FPGA-based dynamic partial reconfiguration A Becher, F Bauer, D Ziener, J Teich 2014 24th International Conference on Field Programmable Logic and …, 2014 | 56 | 2014 |
A self-adaptive SEU mitigation system for FPGAs with an internal block RAM radiation particle sensor R Glein, B Schmidt, F Rittner, J Teich, D Ziener 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom …, 2014 | 48 | 2014 |
A co-design approach for accelerated SQL query processing via FPGA-based data filtering A Becher, D Ziener, K Meyer-Wegener, J Teich 2015 International Conference on Field Programmable Technology (FPT), 192-195, 2015 | 41 | 2015 |
Using the power side channel of FPGAs for communication D Ziener, F Baueregger, J Teich 2010 18th IEEE Annual International Symposium on Field-Programmable Custom …, 2010 | 36 | 2010 |
FPGA core watermarking based on power signature analysis D Ziener, J Teich 2006 IEEE International Conference on Field Programmable Technology, 205-212, 2006 | 33 | 2006 |
Reliability of space-grade vs. COTS SRAM-based FPGA in N-modular redundancy R Glein, F Rittner, A Becher, D Ziener, J Frickel, J Teich, A Heuberger 2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 1-8, 2015 | 29 | 2015 |
Throughput optimizations for FPGA-based deep neural network inference T Posewsky, D Ziener Microprocessors and microsystems 60, 151-161, 2018 | 28 | 2018 |
Symbolic design space exploration for multi-mode reconfigurable systems S Wildermann, F Reimann, D Ziener, J Teich Proceedings of the seventh IEEE/ACM/IFIP international conference on …, 2011 | 28 | 2011 |
FAU: Fast and error-optimized approximate adder units on LUT-Based FPGAs J Echavarria, S Wildermann, A Becher, J Teich, D Ziener 2016 International Conference on Field-Programmable Technology (FPT), 213-216, 2016 | 27 | 2016 |
Stress-aware module placement on reconfigurable devices J Angermeier, D Ziener, M Glaß, J Teich 2011 21st International Conference on Field Programmable Logic and …, 2011 | 27 | 2011 |
Watermarking Apparatus, Software Enabling an Implementation of an Electronic Circuit Comprising a Watermark, Method for Detecting a Watermark and Apparatus for Detecting a … D Ziener, J Teich US Patent App. 11/551,213, 2006 | 25* | 2006 |
A dynamic reconfigurable architecture for hybrid spiking and convolutional fpga-based neural network designs H Irmak, F Corradi, P Detterer, N Alachiotis, D Ziener Journal of Low Power Electronics and Applications 11 (3), 32, 2021 | 24 | 2021 |