| Instructions and logic for vector multiply add with zero skipping S Pal, S Avancha, I Bhati, WY Chen, D Das, A Garg, CS Gurram, J Gu, ... US Patent 11,669,329, 2023 | | 2023 |
| Astra-sim2. 0: Modeling hierarchical networks and disaggregated systems for large-model training at scale W Won, T Heo, S Rashidi, S Sridharan, S Srinivasan, T Krishna 2023 IEEE International Symposium on Performance Analysis of Systems and …, 2023 | 25 | 2023 |
| TACOS: Topology-aware collective algorithm synthesizer for distributed training W Won, M Elavazhagan, S Srinivasan, A Durg, S Gupta, T Krishna arXiv preprint arXiv 2304, 2023 | 3 | 2023 |
| A highly-efficient error detection technique for general matrix multiplication using tiled processing on SIMD architecture CS Mummidi, S Bal, BF Goldstein, S Srinivasan, S Kundu 2022 IEEE 40th International Conference on Computer Design (ICCD), 529-536, 2022 | 3 | 2022 |
| Themis: A network bandwidth-aware collective scheduling policy for distributed training of dl models S Rashidi, W Won, S Srinivasan, S Sridharan, T Krishna Proceedings of the 49th Annual International Symposium on Computer …, 2022 | 27 | 2022 |
| Exploring multi-dimensional hierarchical network topologies for efficient distributed training of trillion parameter dl models W Won, S Rashidi, S Srinivasan, T Krishna arXiv preprint arXiv:2109.11762, 2021 | 3 | 2021 |
| Enabling compute-communication overlap in distributed deep learning training platforms S Rashidi, M Denton, S Sridharan, S Srinivasan, A Suresh, J Nie, ... 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture …, 2021 | 39 | 2021 |
| Extending sparse tensor accelerators to support multiple compression formats E Qin, G Jeong, W Won, SC Kao, H Kwon, S Srinivasan, D Das, GE Moon, ... 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS …, 2021 | 16 | 2021 |
| A lightweight error-resiliency mechanism for deep neural networks BF Goldstein, VC Ferreira, S Srinivasan, D Das, AS Nery, S Kundu, ... 2021 22nd International Symposium on Quality Electronic Design (ISQED), 311-316, 2021 | 15 | 2021 |
| Enabling compute-communication overlap in distributed training platforms S Rashidi, S Sridharan, S Srinivasan, M Denton, A Suresh, J Nie, ... Procedings of 48th International Symposium on Computer Architecture (ISCA), 2021 | | 2021 |
| Optimizing deep learning recommender systems training on cpu cluster architectures D Kalamkar, E Georganas, S Srinivasan, J Chen, M Shiryaev, A Heinecke SC20: International Conference for High Performance Computing, Networking …, 2020 | 46 | 2020 |
| Astra-sim: Enabling sw/hw co-design exploration for distributed dl training platforms S Rashidi, S Sridharan, S Srinivasan, T Krishna 2020 IEEE International Symposium on Performance Analysis of Systems and …, 2020 | 53 | 2020 |
| MINT: Microarchitecture for Efficient and Interchangeable CompressioN Formats on Tensor Algebra. E Qin, G Jeong, W Won, SC Kao, H Kwon, S Srinivasan, D Das, GE Moon, ... Sandia National Lab.(SNL-NM), Albuquerque, NM (United States), 2020 | | 2020 |
| Reliability evaluation of compressed deep learning models BF Goldstein, S Srinivasan, D Das, K Banerjee, L Santiago, VC Ferreira, ... 2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS), 1-5, 2020 | 29 | 2020 |
| Sigma: A sparse and irregular gemm accelerator with flexible interconnects for dnn training E Qin, A Samajdar, H Kwon, V Nadella, S Srinivasan, D Das, B Kaul, ... 2020 IEEE International Symposium on High Performance Computer Architecture …, 2020 | 433 | 2020 |
| Efficient communication acceleration for next-gen scale-up deep learning training platforms S Rashidi, S Sridharan, S Srinivasan, M Denton, T Krishna arXiv preprint, 2020 | 1 | 2020 |
| Training google neural machine translation on an intel cpu cluster DD Kalamkar, K Banerjee, S Srinivasan, S Sridharan, E Georganas, ... 2019 IEEE International Conference on Cluster Computing (CLUSTER), 1-10, 2019 | 8 | 2019 |
| K-tanh: Efficient tanh for deep learning A Kundu, A Heinecke, D Kalamkar, S Srinivasan, EC Qin, NK Mellempudi, ... arXiv preprint arXiv:1909.07729, 2019 | 2 | 2019 |
| High performance scalable FPGA accelerator for deep neural networks S Srinivasan, P Janedula, S Dhoble, S Avancha, D Das, N Mellempudi, ... arXiv preprint arXiv:1908.11809, 2019 | 5 | 2019 |
| Mixed precision training with 8-bit floating point N Mellempudi, S Srinivasan, D Das, B Kaul arXiv preprint arXiv:1905.12334, 2019 | 76 | 2019 |
