An analog circuit approach for optimal damping of inter-area oscillations using wide area control of power converters P Agnihotri, AM Kulkarni, AM Gole, A Sinkar 2019 IEEE Canadian Conference of Electrical and Computer Engineering (CCECE …, 2019 | 1 | 2019 |
A comparative study of master-slave control and virtual synchronous machine control for parallel VSC-HVDC links feeding passive loads on offshore platforms C Jiang, AD Sinkar, MK Das, AM Gole, V Pathirana 15th IET International Conference on AC and DC Power Transmission (ACDC 2019 …, 2019 | 3 | 2019 |
Effects of time delay, DC offset, and truncation errors on interfacing of a phase-locked loop (PLL) with a real-time simulator for controller hardware-in-loop (CHIL) simulation Y Yi, AD Sinkar, AM Gole IET Digital Library, 2019 | | 2019 |
VR-scale: Runtime dynamic phase scaling of processor voltage regulators for improving power efficiency H Asghari-Moghaddam, HR Ghasemi, AA Sinkar, I Paul, NS Kim Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 5 | 2016 |
Quantitative comparison of the power reduction techniques for samsung reconfigurable processor H Kim, S Ryu, A Sinkar, NS Kim 2014 IEEE International Symposium on Circuits and Systems (ISCAS), 1736-1739, 2014 | 1 | 2014 |
Maximizing throughput of power/thermal-constrained processors by balancing power consumption of cores AA Sinkar, H Wang, NS Kim Fifteenth International Symposium on Quality Electronic Design, 633-638, 2014 | 6 | 2014 |
Improving platform energy-chip area trade-off in near-threshold computing environment H Wang, AA Sinkar, NS Kim 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 318-325, 2013 | 7 | 2013 |
Low-cost per-core voltage domain support for power-constrained high-performance processors AA Sinkar, HR Ghasemi, MJ Schulte, UR Karpuzcu, NS Kim IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (4), 747-758, 2013 | 42 | 2013 |
Energysmart: Toward energy-efficient manycores for near-threshold computing UR Karpuzcu, A Sinkar, NS Kim, J Torrellas 2013 IEEE 19th International Symposium on High Performance Computer …, 2013 | 96 | 2013 |
Cost-effective power delivery to support per-core voltage domains for power-constrained processors HR Ghasemi, AA Sinkar, MJ Schulte, NS Kim Proceedings of the 49th Annual Design Automation Conference, 56-61, 2012 | 36 | 2012 |
Clamping virtual supply voltage of power-gated circuits for active leakage reduction and gate-oxide reliability A Sinkar, T Park, NS Kim IEEE transactions on very large scale integration (VLSI) systems 21 (3), 580-584, 2012 | 2 | 2012 |
Workload-aware voltage regulator optimization for power efficient multi-core processors AA Sinkar, H Wang, NS Kim 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2012 | 24 | 2012 |
Improving Performance, Power Efficiency, Yield, and Reliability Using Programmable Power-gating Techniques AA Sinkar The University of Wisconsin-Madison, 2012 | | 2012 |
Maximizing frequency and yield of power-constrained designs using programmable power-gating NS Kim, A Sinkar, J Seomun, Y Shin IEEE transactions on very large scale integration (VLSI) systems 20 (10 …, 2011 | 1 | 2011 |
AVS-aware power-gate sizing for maximum performance and power efficiency of power-constrained processors A Sinkar, NS Kim 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 725-730, 2011 | 1 | 2011 |
Combating aging with the colt duty cycle equalizer E Gunadi, AA Sinkar, NS Kim, MH Lipasti 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 103-114, 2010 | 76 | 2010 |
Analyzing and minimizing effects of temperature variation and NBTI on active leakage power of power-gated circuits A Sinkar, NS Kim 2010 11th International Symposium on Quality Electronic Design (ISQED), 791-796, 2010 | 15 | 2010 |
Statistical static timing analysis considering leakage variability in power gated designs MJ Anderson, A Davoodi, J Lee, A Sinkar, NS Kim Proceedings of the 2009 ACM/IEEE international symposium on Low power …, 2009 | 1 | 2009 |
Analyzing potential power reduction with adaptive voltage positioning optimized for multicore processors A Sinkar, NS Kim Proceedings of the 2009 ACM/IEEE international symposium on Low power …, 2009 | 9 | 2009 |
Frequency and yield optimization using power gates in power-constrained designs NS Kim, J Seomun, A Sinkar, J Lee, TH Han, K Choi, Y Shin Proceedings of the 2009 ACM/IEEE international symposium on Low power …, 2009 | 14 | 2009 |