| 13th International Workshop on Network on Chip Architectures (NoCArc) A Chakraborty, C Almudéver, D Zhao, D Göhringer, G Ascia, HK Kapoor, ... | | |
| 2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)| 978-1-6654-9747-3/22/$31.00© 2022 IEEE| DOI: 10.1109/IPDPSW55747. 2022.00225 TS Abdelrahman, GS Abhishek, S Abraham, JA Acosta, S Adavally, ... | | |
| A closed loop control based power manager for winoc architectures MS Rusli, A Mineo, M Palesi, G Ascia, V Catania, MN Marsono Proceedings of International Workshop on Manycore Embedded Systems, 60-63, 2014 | 6 | 2014 |
| A CLOSED LOOP POWER MANAGER FOR TRANSMISSION POWER CONTROL IN WIRELESS NETWORK-ON-CHIP ARCHITECTURES MS Rusli, A Mineo, M Palesi, G Ascia, V Catania, OC Yee, MN Marsono Jurnal Teknologi 75 (1), 2015 | | 2015 |
| A closed loop transmitting power self-calibration scheme for energy efficient winoc architectures A Mineo, MS Rusli, M Palesi, G Ascia, V Catania, MN Marsono 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 513-518, 2015 | 16 | 2015 |
| A data dependent approach to instruction level power estimation D Sarta, D Trifone, G Ascia Proceedings IEEE Alessandro Volta Memorial Workshop on Low-Power Design, 182-190, 1999 | 73 | 1999 |
| A data dependent model for software power estimation: Un modello dipendente dai dati per la valutazione del consumo di potenza G Ascia, V Catania, M Palesi Rivista di Informatica 31 (3), 231-244, 2001 | | 2001 |
| A dedicated parallel processor for fuzzy computation G Ascia, V Catania Proceedings of 6th International Fuzzy Systems Conference 2, 787-792, 1997 | 7 | 1997 |
| A framework for a parallel architecture dedicated to soft computing G Ascia, V Catania Proceedings Eleventh International Conference on VLSI Design, 318-321, 1998 | 4 | 1998 |
| A framework for design space exploration of parameterized VLSI systems G Ascia, V Catania, M Palesi Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design …, 2002 | 21 | 2002 |
| A fuzzy buffer management scheme for ATM and IP networks G Ascia, V Catania, G Ficili, D Panno Proceedings IEEE INFOCOM 2001. Conference on Computer Communications …, 2001 | 31 | 2001 |
| A fuzzy system index to preserve interpretability in deep tuning of fuzzy rule based classifiers A Di Nuovo, G Ascia Journal of Intelligent & Fuzzy Systems 25 (2), 493-504, 2013 | 4 | 2013 |
| A GA-based design space exploration framework for parameterized system-on-a-chip platforms G Ascia, V Catania, M Palesi IEEE Transactions on Evolutionary Computation 8 (4), 329-346, 2004 | 84 | 2004 |
| A general purpose processor oriented to fuzzy reasoning G Ascia, V Catania 10th IEEE International Conference on Fuzzy Systems.(Cat. No. 01CH37297) 1 …, 2001 | 9 | 2001 |
| A genetic approach to bus encoding G Ascia, V Catania, M Palesi, A Parlato Proceedings of International Conference on Very Large Scale Integration of …, 2003 | | 2003 |
| A genetic bus encoding technique for power optimization of embedded systems G Ascia, V Catania, M Palesi Integrated Circuit and System Design. Power and Timing Modeling …, 2003 | 4 | 2003 |
| A high performance processor for applications based on fuzzy logic G Ascia, V Catania FUZZ-IEEE'99. 1999 IEEE International Fuzzy Systems. Conference Proceedings …, 1999 | 10 | 1999 |
| A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip. G Ascia, V Catania, M Palesi J. Univers. Comput. Sci. 12 (4), 370-394, 2006 | 62 | 2006 |
| A multiobjective genetic approach for system-level exploration in parameterized systems-on-a-chip G Ascia, V Catania, M Palesi IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2005 | 43 | 2005 |
| A multiobjective genetic fuzzy approach for intelligent system-level exploration in parameterized vliw processor design G Ascia, V Catania, AG Di Nuovo, M Palesi, D Patti 2006 IEEE International Conference on Evolutionary Computation, 1736-1743, 2006 | 3 | 2006 |
