| A case study in hardware Trojan design and implementation A Baumgarten, M Steffen, M Clausman, J Zambreno International Journal of Information Security 10, 1-14, 2011 | 103 | 2011 |
| A chaotic encryption scheme for real-time embedded systems: design and implementation A Pande, J Zambreno Telecommunication Systems 52, 551-561, 2013 | 88 | 2013 |
| A configurable architecture for sparse LU decomposition on matrices with arbitrary patterns X Wang, PH Jones, J Zambreno ACM SIGARCH Computer Architecture News 43 (4), 76-81, 2016 | 5 | 2016 |
| A fast Markov decision process-based algorithm for collision avoidance in urban air mobility J Bertram, P Wei, J Zambreno IEEE transactions on intelligent transportation systems 23 (9), 15420-15433, 2022 | 17 | 2022 |
| A floating-point accumulator for FPGA-based high performance computing applications S Sun, J Zambreno Proceedings of the International Conference on Field-Programmable Technology …, 2009 | 46 | 2009 |
| A hardware pipeline for accelerating ray traversal algorithms on streaming processors M Steffen, J Zambreno 2010 IEEE 8th Symposium on Application Specific Processors (SASP), 22-29, 2010 | 4 | 2010 |
| A high performance systolic architecture for k-NN classification KR Townsend, P Jones, J Zambreno 2014 Twelfth ACM/IEEE Conference on Formal Methods and Models for Codesign …, 2014 | 2 | 2014 |
| A modified sliding window architecture for efficient bram resource utilization M Qasaimeh, J Zambreno, PH Jones 2017 IEEE International Parallel and Distributed Processing Symposium …, 2017 | 3 | 2017 |
| A multi-faceted approach to FPGA-based Trojan circuit detection M Patterson, A Mills, R Scheel, J Tillman, E Dye, J Zambreno 2013 IEEE 31st VLSI Test Symposium (VTS), 1-4, 2013 | 7 | 2013 |
| A multi-phase approach to floating-point compression KR Townsend, J Zambreno 2015 IEEE International Conference on Electro/Information Technology (EIT …, 2015 | 7 | 2015 |
| A project-based embedded systems design course using a reconfigurable SoC platform D Roggow, P Uhing, P Jones, J Zambreno 2015 IEEE International Conference on Microelectronics Systems Education …, 2015 | 20 | 2015 |
| A reconfigurable architecture for QR decomposition using a hybrid approach X Wang, P Jones, J Zambreno 2014 IEEE Computer Society Annual Symposium on VLSI, 541-546, 2014 | 5 | 2014 |
| A reconfigurable architecture for secure multimedia delivery A Pande, J Zambreno 2010 23rd International Conference on VLSI Design, 258-263, 2010 | 13 | 2010 |
| A Reconfigurable Architecture for the Detection of Strongly Connected Components OG Attia, KR Townsend, PH Jones, J Zambreno ACM Transactions on Reconfigurable Technology and Systems (TRETS) 9 (2), 1-19, 2015 | 2 | 2015 |
| A run-time reconfigurable architecture for embedded program flow verification J Zambreno, T Anish, A Choudhary NATO SECURITY THROUGH SCIENCE SERIES D-INFORMATION AND COMMUNICATION …, 2006 | 6 | 2006 |
| A runtime configurable hardware architecture for computing histogram-based feature descriptors M Qasaimeh, J Zambreno, PH Jones 2018 28th International Conference on Field Programmable Logic and …, 2018 | 7 | 2018 |
| A Scalable Unsegmented Multiport Memory for FPGA-Based Systems P Jones, J Zambreno | | 2015 |
| A Scalable Unsegmented Multiport Memory for FPGA‐Based Systems KR Townsend, OG Attia, PH Jones, J Zambreno International Journal of Reconfigurable Computing 2015 (1), 826283, 2015 | 13 | 2015 |
| A software configurable and parallelized coprocessor architecture for LQR control P Zhang, A Mills, J Zambreno, PH Jones 2015 International Conference on ReConFigurable Computing and FPGAs …, 2015 | 11 | 2015 |
| A software configurable coprocessor-based state-space controller A Mills, P Zhang, S Vyas, J Zambreno, PH Jones 2015 25th International Conference on Field Programmable Logic and …, 2015 | 7 | 2015 |
Phillip H. JonesIowa state University在 iastate.edu 的电子邮件经过验证
