John P Hayes 个人学术档案 - 学术资源搜索

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	总计	2019 年至今
引用	18646	3899
h 指数	71	32
i10 指数	222	74

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Igor L. MarkovSynopsys在 synopsys.com 的电子邮件经过验证
Armin AlaghiUniversity of Washington在 cs.washington.edu 的电子邮件经过验证
Ilia PolianUniversity of Stuttgart在 polian.de 的电子邮件经过验证
Brian MurrayZF Friedrichshafen在 zf.com 的电子邮件经过验证
Smita KrishnaswamyYale University在 yale.edu 的电子邮件经过验证
Trevor MudgeBredt Family Professor of Engineering, University of Michigan在 eecs.umich.edu 的电子邮件经过验证
Krishnendu ChakrabartyFulton Professor of Microelectronics, School of Electrical and Computer and Energy Engineering在 asu.edu 的电子邮件经过验证
Vivek ShendeSyddansk Universitet & UC Berkeley在 math.berkeley.edu 的电子邮件经过验证
Nagarajan KandasamyProfessor of computer engineering, Drexel University在 drexel.edu 的电子邮件经过验证
Shantanu DuttProfessor of Electrical & Computer Engineering在 ece.uic.edu 的电子邮件经过验证
Hussain Al-AsaadProfessor of Electrical and Computer Engineering, UC Davis在 ucdavis.edu 的电子邮件经过验证
Bernd BeckerProfessor of Computer Science, University of Freiburg在 informatik.uni-freiburg.de 的电子邮件经过验证
Paishun TingUniversity of Michigan - Ann Arbor在 umich.edu 的电子邮件经过验证
Quentin StoutProfessor of Computer Science, University of Michigan在 umich.edu 的电子邮件经过验证
Te-Hsuan ChenUniversity of Michigan在 umich.edu 的电子邮件经过验证
Weikang QianUniversity of Michigan-SJTU Joint Institute, Shanghai Jiao Tong University在 sjtu.edu.cn 的电子邮件经过验证
HyungWon KimProfessor of Electronics Engineering, Chungbuk National University在 cbnu.ac.kr 的电子邮件经过验证
Timothy James BakerResearch Fellow, Michigan Medicine在 bakertim.com 的电子邮件经过验证
John Paul ShenCarnegie Mellon University在 cmu.edu 的电子邮件经过验证
Stephen M PlazaProject and Software Engineering Manager, Janelia Farm Research Campus在 janelia.hhmi.org 的电子邮件经过验证

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John P Hayes

Professor of EECS, University of Michigan

在 umich.edu 的电子邮件经过验证 - 首页

stochastic computing computer architecture digital design VLSI emerging technologies


标题按引用次数排序按年份排序按标题排序	引用次数引用次数	年份
0n:(Vhigh 0Vlow) RDS Blanton, JP Hayes IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 8 (2), 221, 2000		2000
2.2 Stochastic, Approximate and Neural Computing F Neugebauer, I Polian, J Hayes
2009 technical paper reviewers E Cole Jr, D Conti, B Cory, E Cota, A Crouch, A InterTech, D Czysz, ...
4757503 Self-testing dynamic RAM JP Hayes, Y You Microelectronics Reliability 29 (2), 294, 1989		1989
50th Annual Device Research Conference P Asbeck, J Hayes, J Rosenberg, D Bloom, T Ito, J Sturm, P Chow, ... IEEE Transactions on Electron Devices 39 (11), 1992	1	1992
A 3.6 mW 2.4-GHz multi-channel super-regenerative receiver in 130nm CMOS JY Chen, MP Flynn, JP Hayes Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005 …, 2005	15	2005
A 900 Mbps single-channel capacitive I/O link for wireless wafer-level testing of integrated circuits DY Lee, DD Wentzloff, JP Hayes IEEE Asian Solid-State Circuits Conference 2011, 153-156, 2011	3	2011
A calculus for testing complex digital systems JP Hayes Proc. 10th Fault-Tolerant Computing Symposium, 115-120, 1980	7	1980
A family of logical fault models for reversible circuits I Polian, T Fiehn, B Becker, JP Hayes 14th Asian Test Symposium (ATS'05), 422-427, 2005	153	2005
A fault model for function and delay testing J Yi, JP Hayes IEEE European Test Workshop, 2001., 27-34, 2001	25	2001
A fault simulation methodology for VLSI JP Hayes 19th Design Automation Conference, 393-399, 1982	24	1982
A fault-tolerant communication scheme for hypercube computers TC Lee, JP Hayes IEEE Transactions on Computers 41 (10), 1242-1256, 1992	225	1992
A Fully Integrated Auto-Calibrated Super-Regenerative Receiver in 0.13-CMOS JY Chen, MP Flynn, JP Hayes IEEE Journal of Solid-State Circuits 42 (9), 1976-1985, 2007	196	2007
A fully integrated auto-calibrated superregenerative receiver JY Chen, MP Flynn, JP Hayes 2006 IEEE International Solid State Circuits Conference-Digest of Technical …, 2006	33	2006
A functional approach to testing bit-sliced microprocessors Sridhar, Hayes IEEE Transactions on Computers 100 (8), 563-571, 1981	92	1981
A graph model for fault-tolerant computing systems Hayes IEEE Transactions on computers 100 (9), 875-884, 1976	432	1976
A hierarchical technique for minimum-width layout of two-dimensional CMOS cells A Gupta, JP Hayes Proceedings Tenth International Conference on VLSI Design, 15-20, 1997	8	1997
A hierarchical test generation methodology for digital circuits D Bhattacharya, JP Hayes Journal of Electronic Testing 1, 103-123, 1990	42	1990
A local-sparing design methodology for fault-tolerant multiprocessors S Dutt, JP Hayes Computers & Mathematics with Applications 34 (11), 25-50, 1997	5	1997
A logic design theory for VLSI JP Hayes California Institute of Technology, 1981	21	1981

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