| Secure state estimation for cyber-physical systems under sensor attacks: A satisfiability modulo theory approach Y Shoukry, P Nuzzo, A Puggelli, AL Sangiovanni-Vincentelli, SA Seshia, ... IEEE Transactions on Automatic Control 62 (10), 4917-4932, 2017 | 317 | 2017 |
| An agile approach to building RISC-V microprocessors Y Lee, A Waterman, H Cook, B Zimmer, B Keller, A Puggelli, J Kwak, ... ieee Micro 36 (2), 8-20, 2016 | 157 | 2016 |
| Data-Driven Probabilistic Modeling and Verification of Human Driver Behavior D Sadigh, KD Campbell, AAA Puggelli, W Li, V Shia, R Bajcsy, ... AAAI 2014 Spring Symposia - FORMAL VERIFICATION AND MODELING IN HUMAN …, 2013 | 105 | 2013 |
| Polynomial-Time Verification of PCTL Properties of MDPs with Convex Uncertainties A Puggelli, W Li, AL Sangiovanni-Vincentelli, SA Seshia Computer Aided Verification (CAV), 527-542, 2013 | 105 | 2013 |
| BAG: A designer-oriented integrated framework for the development of AMS circuit generators J Crossley, A Puggelli, HP Le, B Yang, R Nancollas, K Jung, L Kong, ... 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 74-81, 2013 | 94 | 2013 |
| A RISC-V vector processor with simultaneous-switching switched-capacitor DC–DC converters in 28 nm FDSOI B Zimmer, Y Lee, A Puggelli, J Kwak, R Jevtić, B Keller, S Bailey, ... IEEE Journal of Solid-State Circuits 51 (4), 930-942, 2016 | 82 | 2016 |
| CalCS: SMT solving for non-linear convex constraints P Nuzzo, A Puggelli, SA Seshia, A Sangiovanni-Vincentelli Formal Methods in Computer Aided Design, 71-79, 2010 | 82 | 2010 |
| A RISC-V processor SoC with integrated power management at submicrosecond timescales in 28 nm FD-SOI B Keller, M Cochet, B Zimmer, J Kwak, A Puggelli, Y Lee, M Blagojević, ... IEEE Journal of Solid-State Circuits 52 (7), 1863-1875, 2017 | 55 | 2017 |
| A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI B Zimmer, Y Lee, A Puggelli, J Kwak, R Jevtic, B Keller, S Bailey, ... 2015 Symposium on VLSI Circuits (VLSI Circuits), C316-C317, 2015 | 54 | 2015 |
| Sound and complete state estimation for linear dynamical systems under sensor attacks using satisfiability modulo theory solving Y Shoukry, A Puggelli, P Nuzzo, AL Sangiovanni-Vincentelli, SA Seshia, ... 2015 American Control Conference (ACC), 3818-3823, 2015 | 42 | 2015 |
| Time-to-digital converter with 3-ps resolution and digital linearization algorithm M Zanuso, S Levantino, A Puggelli, C Samori, AL Lacaita 2010 Proceedings of ESSCIRC, 262-265, 2010 | 36 | 2010 |
| Methodology for the design of analog integrated interfaces using contracts P Nuzzo, A Sangiovanni-Vincentelli, X Sun, A Puggelli IEEE Sensors Journal 12 (12), 3329-3345, 2012 | 34 | 2012 |
| Feedback control for efficient high-speed battery charging AAA Puggelli, T Li, H Meyvaert, BJ Rodgers, Z Li, W Kim US Patent 10,243,457, 2019 | 33 | 2019 |
| Feedback control in hybrid voltage regulators HP Le, J CROSSLEY, A PUGGELLI, W Kim US Patent App. 14/508,229, 2015 | 33 | 2015 |
| Routing-Aware Design of Indoor Wireless Sensor Networks Using an Interactive Tool A Puggelli, MMR Mozumdar, L Lavagno, AL Sangiovanni-Vincentelli IEEE, 2013 | 31 | 2013 |
| Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking Y Lee, B Zimmer, A Waterman, A Puggelli, J Kwak, R Jevtic, B Keller, ... 2015 IEEE Hot Chips 27 Symposium (HCS), 1-45, 2015 | 24 | 2015 |
| Apparatus, systems and methods for reconfigurable dickson star switched capacitor voltage regulator AAA PUGGELLI, T Li, W Kim, J CROSSLEY, HP Le | 22 | 2019 |
| Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC B Keller, M Cochet, B Zimmer, Y Lee, M Blagojevic, J Kwak, A Puggelli, ... ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 269-272, 2016 | 22 | 2016 |
| Imhotep-SMT: A satisfiability modulo theory solver for secure state estimation Y Shoukry, P Nuzzo, A Puggelli, AL Sangiovanni-Vincentelli, SA Seshia, ... 13th International Workshop on Satisfiability Modulo Theories (SMT), 3-13, 2015 | 21 | 2015 |
| Are logic synthesis tools robust? A Puggelli, T Welp, A Kuehlmann, A Sangiovanni-Vincentelli Proceedings of the 48th Design Automation Conference, 633-638, 2011 | 18 | 2011 |
Alberto Sangiovanni VincentelliProfessor of EECS, University of California, Berkeley在 eecs.berkeley.edu 的电子邮件经过验证
