| A 14b 80 ms/s sar adc with 73.6 db sndr in 65 nm cmos R Kapusta, J Shen, S Decker, H Li, E Ibaragi, H Zhu IEEE Journal of Solid-State Circuits 48 (12), 3059-3066, 2013 | 199 | 2013 |
| A 16-bit 16-MS/s SAR ADC with on-chip calibration in 55-nm CMOS J Shen, A Shikata, LD Fernando, N Guthrie, B Chen, M Maddox, ... IEEE Journal of Solid-State Circuits 53 (4), 1149-1160, 2018 | 127 | 2018 |
| Edge-pursuit comparator: An energy-scalable oscillator collapse-based comparator with application in a 74.1 dB SNDR and 20 kS/s 15 b SAR ADC M Shim, S Jeong, PD Myers, S Bang, J Shen, C Kim, D Sylvester, ... IEEE Journal of Solid-State Circuits 52 (4), 1077-1090, 2017 | 87 | 2017 |
| A 0.5-V 8-bit 10-Ms/s pipelined ADC in 90-nm CMOS J Shen, PR Kinget IEEE journal of solid-state circuits 43 (4), 787-795, 2008 | 82 | 2008 |
| A 16 bit linear passive-charge-sharing SAR ADC in 55nm CMOS M Maddox, B Chen, M Coln, R Kapusta, J Shen, L Fernando 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), 153-156, 2016 | 31 | 2016 |
| A 12-Bit 31.1- W 1-MS/s SAR ADC With On-Chip Input-Signal-Independent Calibration Achieving 100.4-dB SFDR Using 256-fF Sampling Capacitance J Shen, A Shikata, A Liu, B Chen, F Chalifoux IEEE Journal of Solid-State Circuits 54 (4), 937-947, 2018 | 30 | 2018 |
| Self-timed digital-to-analog converter R Kapusta, S Junhua, D Lin US Patent 8,456,340, 2013 | 29 | 2013 |
| Current-charge-pump residue amplification for ultra-low-power pipelined ADCs J Shen, PR Kinget IEEE Transactions on Circuits and Systems II: Express Briefs 58 (7), 412-416, 2011 | 25 | 2011 |
| Background calibration of ADC reference voltage due to input signal dependency S Junhua, RA Kapusta, EC Guthrie US Patent 8,981,972, 2015 | 15 | 2015 |
| ADC background calibration with dual conversions H Li, S Junhua, M Mueck, MCW Coln US Patent 9,608,655, 2017 | 12 | 2017 |
| Systems and methods for providing a pipelined analog-to-digital converter J Kuppambatti, S Junhua, P Kinget US Patent 9,143,144, 2015 | 10 | 2015 |
| SAR ADCs with dedicated reference capacitor for each bit capacitor S Junhua, MD Maddox, RA Kapusta US Patent 10,205,462, 2019 | 9 | 2019 |
| Analog-to-digital converter speed calibration techniques A Shikata, S Junhua, A Liu US Patent 10,454,492, 2019 | 6 | 2019 |
| Measurement method and apparatus for ADC calibration RA Kapusta, S Junhua US Patent 8,514,114, 2013 | 6 | 2013 |
| Circuits and methods for implementing a residue amplifier S Junhua, P Kinget US Patent 9,246,504, 2016 | 5 | 2016 |
| Accuracy enhancement techniques for ADCs S Junhua, RA Kapusta US Patent 9,071,261, 2015 | 5 | 2015 |
| A high image rejection continuous-time IF sigma-delta ADC with time-sharing of input resistors JH Shen, KP Pun, CS Choy, CF Chan 2003 IEEE Conference on Electron Devices and Solid-State Circuits (IEEE Cat …, 2003 | 5 | 2003 |
| Edge pursuit comparator with application in a 74.1 dB SNDR, 20KS/s 15b SAR ADC M Shim, S Jeong, P Myers, S Bang, J Shen, C Kim, D Sylvester, D Blaauw, ... 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 295-296, 2018 | 4 | 2018 |
| SAR ADCs with dedicated reference capacitor for each bit capacitor S Junhua, MD Maddox, RA Kapusta US Patent 10,637,495, 2020 | 2 | 2020 |
| SAR ADC performance optimization with dynamic bit trial settings S Junhua, EC Guthrie US Patent 9,571,114, 2017 | 2 | 2017 |
