| 17.3 A −58dBc-Worst-Fractional-Spur and −234dB-FoMjitter, 5.5GHz Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator … T Seong, Y Lee, C Hwang, J Lee, H Park, KJ Lee, J Choi 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 270-272, 2020 | 30 | 2020 |
| 32.1 A 365fsrms-jitter and-63dBc-Fractional spur 5.3 GHz-ring-DCO-based fractional-N DPLL using a DTC second/third-order nonlinearity cancelation and a probability-density … H Park, C Hwang, T Seong, Y Lee, J Choi 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 442-444, 2021 | 24 | 2021 |
| 17.1 A −240dB-FoMjitter and −115dBc/Hz PN @ 100kHz, 7.7GHz Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Sequence-Rearranged … Y Lee, T Seong, J Lee, C Hwang, H Park, J Choi 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 266-268, 2020 | 16 | 2020 |
| A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC’s Second-/Third-Order Nonlinearity Cancellation and a Probability … C Hwang, H Park, Y Lee, T Seong, J Choi IEEE Journal of Solid-State Circuits 57 (9), 2841-2855, 2022 | 14 | 2022 |
| 23.4 An 82fsrms-Jitter and 22.5mW-Power, 102GHz W-Band PLL Using a Power-Gating Injection-Locked Frequency-Multiplier-Based Phase Detector in 65nm CMOS S Yoo, S Park, S Choi, Y Cho, H Yoon, C Hwang, J Choi 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 330-332, 2021 | 14 | 2021 |
| A low-jitter ring-DCO-based fractional-N digital PLL with a 1/8 DTC-range-reduction technique using a quadruple-timing-margin phase selector H Park, C Hwang, T Seong, J Choi IEEE Journal of Solid-State Circuits 57 (12), 3527-3537, 2022 | 9 | 2022 |
| A 188fsrms-Jitter and −243d8-FoMjitter 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing … C Hwang, H Park, T Seong, J Choi 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 378-380, 2022 | 9 | 2022 |
| A 0.1–1.5-GHz wide harmonic-locking-free delay-locked loop using an exponential DAC S Park, J Kim, C Hwang, H Park, S Yoo, T Seong, J Choi IEEE Microwave and Wireless Components Letters 29 (8), 548-550, 2019 | 8 | 2019 |
| A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier Y Jo, J Kim, Y Shin, H Park, C Hwang, Y Lim, J Choi IEEE Journal of Solid-State Circuits, 2023 | 6 | 2023 |
| Integrated circuit, electronic device including the same, and operating method thereof J Choi, T Seong, Y Lee, C Hwang, P Hangi US Patent 11,271,584, 2022 | 6 | 2022 |
| A 135fsrms-Jitter 0.6-to-7.7GHz LO Generator Using a Single LC-VCO-Based Subsampling PLL and a Ring-Oscillator-Based Sub-Integer-N Frequency Multiplier Y Jo, J Kim, Y Shin, C Hwang, H Park, J Choi 2023 IEEE International Solid-State Circuits Conference (ISSCC), 1-3, 2023 | 5 | 2023 |
| 10.2 A 5.5 μs-Calibration-Time, Low-Jitter, and Compact-Area Fractional-N Digital PLL Using the Recursive-Least-Squares (RLS) Algorithm S Jang, M Chae, H Park, C Hwang, J Choi 2024 IEEE International Solid-State Circuits Conference (ISSCC) 67, 190-192, 2024 | | 2024 |
| INTEGRATED CIRCUIT, ELECTRONIC DEVICE INCLUDING THE SAME, AND OPERATING METHOD THEREOF H Park, C Hwang, Y Lee, T Seong, J Choi US, 2021 | | 2021 |
