A modular design flow for very large design space explorations T Jungeblut, S Lütkemeier, G Sievers, M Porrmann, U Rückert | 84 | 2010 |
CoreVA-MPSoC: A many-core architecture with tightly coupled shared and local data memories J Ax, G Sievers, J Daberkow, M Flasskamp, M Vohrmann, T Jungeblut, ... IEEE Transactions on Parallel and Distributed Systems 29 (5), 1030-1043, 2017 | 35 | 2017 |
Evaluation of Interconnect Fabrics for an Embedded MPSoC in 28 nm FD-SOI G Sievers, J Ax, N Kucza, M Flasskamp, T Jungeblut, W Kelly, ... International Symposium on Circuits and Systems (ISCAS), 1925 - 1928, 2015 | 20 | 2015 |
CoreVA: A configurable resource-efficient VLIW processor architecture B Hübener, G Sievers, T Jungeblut, M Porrmann, U Rückert 2014 12th IEEE International Conference on Embedded and Ubiquitous Computing …, 2014 | 20 | 2014 |
Driving Simulation Technologies for Sensor Simulation in SIL and HIL Environments G Sievers, C Seiger, M Peperhowe, H Krumm, S Graf Driving Simulation Conference Europe 2018 VR, 2018 | 19 | 2018 |
A communication model and partitioning algorithm for streaming applications for an embedded MPSoC W Kelly, M Flaßkamp, G Sievers, J Ax, J Chen, C Klarhorst, C Ragg, ... 2014 International Symposium on System-on-Chip (SoC), 1-6, 2014 | 19 | 2014 |
Design space exploration for memory subsystems of VLIW architectures T Jungeblut, G Sievers, M Porrmann, U Rückert 2010 IEEE Fifth International Conference on Networking, Architecture, and …, 2010 | 17 | 2010 |
Performance Estimation of Streaming Applications for Hierarchical MPSoCs M Flasskamp, G Sievers, J Ax, C Klarhorst, T Jungeblut, W Kelly, M Thies, ... Proceedings of the 2016 Workshop on Rapid Simulation and Performance …, 2016 | 14 | 2016 |
Comparison of shared and private l1 data memories for an embedded mpsoc in 28nm fd-soi G Sievers, J Daberkow, J Ax, M Flasskamp, W Kelly, T Jungeblut, ... 2015 IEEE 9th International Symposium on Embedded Multicore/Many-core …, 2015 | 14 | 2015 |
Pareto-optimal signal processing on low-power microprocessors P Christ, G Sievers, J Einhaus, T Jungeblut, M Porrmann, U Rückert SENSORS, 2013 IEEE, 1-4, 2013 | 9 | 2013 |
System-level analysis of network interfaces for hierarchical mpsocs J Ax, G Sievers, M Flasskamp, W Kelly, T Jungeblut, M Porrmann Proceedings of the 8th International Workshop on Network on Chip …, 2015 | 8 | 2015 |
Design-space exploration of the configurable 32 bit VLIW processor CoreVA for signal processing applications G Sievers, P Christ, J Einhaus, T Jungeblut, M Porrmann, U Rückert 2013 NORCHIP, 1-4, 2013 | 7 | 2013 |
The CoreVA-MPSoC: A multiprocessor platform for software-defined radio G Sievers, B Hübener, J Ax, M Flasskamp, W Kelly, T Jungeblut, ... Computing platforms for software-defined radio, 29-59, 2017 | 6 | 2017 |
Dynamisch rekonfigurierbare Hardware als Basistechnologie für intelligente technische Systeme S Korf, G Sievers, J Ax, D Cozzi, T Jungeblut, J Hagemeyer, M Porrmann, ... Proceedings Wissenschaftsforum 2013 Intelligente Technische Systeme 310, 2013 | 5 | 2013 |
Simulation von Sensoren im SiL-und HiL-Umfeld G Sievers, S Graf, M Peperhowe, C Seiger ATZextra 23 (5), 22-25, 2018 | 3 | 2018 |
TEST SYSTEM FOR A LiDAR SENSOR AND METHOD FOR TESTING A LiDAR SENSOR G Sievers, F Schuette, J Hagemeyer, J Lachmair, D Jungewelter US Patent App. 17/695,147, 2022 | 1 | 2022 |
Module with a serialization unit and improved compatibility with deserialization units of different series G Sievers, J Ax US Patent 11,237,832, 2022 | 1 | 2022 |
Entwurfsraumexploration eng gekoppelter paralleler Rechnerarchitekturen G Sievers | 1 | 2016 |
Resource Efficiency of Scalable Processor Architectures for SDR-based Applications T Jungeblut, J Ax, G Sievers, B Hübener, M Porrmann, U Rückert Proc. of the Radar, Communication and Measurement Conference (RADCOM), 2011 | 1 | 2011 |
Computer system for controlling peripheral devices N Nottbeck, H Bathke, G Sievers US Patent App. 18/129,438, 2024 | | 2024 |