| The reuse cache: Downsizing the shared last-level cache J Albericio, P Ibáñez, V Viñals, JM Llabería Proceedings of the 46th Annual IEEE/ACM International Symposium on …, 2013 | 68 | 2013 |
| Store buffer design in first-level multibanked data caches EF Torres, P Ibánez, V Viñals, JM Llabería 32nd International Symposium on Computer Architecture (ISCA'05), 469-480, 2005 | 51 | 2005 |
| Memory hierarchy characterization of SPEC CPU2006 and SPEC CPU2017 on the Intel Xeon Skylake-SP A Navarro-Torres, J Alastruey-Benedé, P Ibáñez-Marín, V Viñals-Yúfera Plos one 14 (8), e0220135, 2019 | 35 | 2019 |
| Concertina: Squeezing in cache content to operate at near-threshold voltage A Ferreron, D Suarez-Gracia, J Alastruey-Benede, T Monreal-Arnal, ... IEEE Transactions on Computers 65 (3), 755-769, 2015 | 32 | 2015 |
| Exploiting reuse locality on inclusive shared last-level caches J Albericio, P Ibánez, V Viñals, JM Llabería ACM Transactions on Architecture and Code Optimization (TACO) 9 (4), 1-19, 2013 | 27 | 2013 |
| Multi-level adaptive prefetching based on performance gradient tracking LM Ramos, JL Briz, PE Ibáñez, V Viñals Journal of Instruction-Level Parallelism 13, 1-14, 2011 | 26 | 2011 |
| Berti: an accurate local-delta data prefetcher A Navarro-Torres, B Panda, J Alastruey-Benedé, P Ibáñez, ... 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO), 975-991, 2022 | 25 | 2022 |
| A review of High Performance Computing foundations for scientists P García-Risueño, PE Ibáñez International journal of modern physics C 23 (07), 1230001, 2012 | 23 | 2012 |
| ABS: A low-cost adaptive controller for prefetching in a banked shared last-level cache J Albericio, R Gran, P Ibánez, V Viñals, JM Llabería ACM Transactions on Architecture and Code Optimization (TACO) 8 (4), 1-20, 2012 | 16 | 2012 |
| Accelerating sequence alignments based on FM-index using the Intel KNL processor JM Herruzo, S González-Navarro, P Ibanez-Marin, V Vinals-Yufera, ... IEEE/ACM transactions on computational biology and bioinformatics 17 (4 …, 2018 | 15 | 2018 |
| Characterization and improvement of load/store cache-based prefetching P Ibáñez, V Viñals, JL Briz, MJ Garzarán Proceedings of the 12th international conference on Supercomputing, 369-376, 1998 | 15 | 1998 |
| Characterization of Apache web server with Specweb2005 A Bosque, P Ibañez, V Viñals, P Stenström, JM Llabería Proceedings of the 2007 workshop on Memory performance: Dealing with …, 2007 | 12 | 2007 |
| Data prefetching in a cache hierarchy with high bandwidth and capacity LM Ramos, JL Briz, PE Ibáñez, V Viñals ACM SIGARCH Computer Architecture News 35 (4), 37-44, 2007 | 12 | 2007 |
| A methodology to characterize critical section bottlenecks in dsm multiprocessors B Sahelices, P Ibánez, V Viñals, JM Llabería European Conference on Parallel Processing, 149-161, 2009 | 11 | 2009 |
| Compressed sparse FM-index: Fast sequence alignment using large k-steps R Langarita, A Armejach, J Setoain, P Ibanez-Marin, J Alastruey-Benedé, ... IEEE/ACM Transactions on Computational Biology and Bioinformatics 19 (1 …, 2020 | 9 | 2020 |
| Software demand, hardware supply J Alastruey, JL Briz, P Ibáñez, V Viñals IEEE Micro 26 (4), 72-82, 2006 | 9 | 2006 |
| Hardware prefetching in bus-based multiprocessors: pattern characterization and cost-effective hardware MJ Garzaran, JL Brit, PE Ibáñez, V Vinals Proceedings Ninth Euromicro Workshop on Parallel and Distributed Processing …, 2001 | 9 | 2001 |
| Reuse detector: Improving the management of STT-RAM SLLCs R Rodríguez-Rodríguez, J Díaz, F Castro, P Ibáñez, D Chaver, V Viñals, ... The Computer Journal 61 (6), 856-880, 2018 | 8 | 2018 |
| Warm Time-sampling: Fast and Accurate Cycle-level Simulation of Cache Memory L Jimeno, P Ibáñez, V Viñals Proc. of the 22nd Euromicro Conf. Short Contrib. pp, 39-44, 1996 | 8* | 1996 |
| Low-cost adaptive data prefetching LM Ramos, JL Briz, PE Ibáñez, V Viñals Euro-Par 2008–Parallel Processing: 14th International Euro-Par Conference …, 2008 | 7 | 2008 |
Víctor Viñals-YúferaUniversidad de Zaragoza在 unizar.es 的电子邮件经过验证
