| DNN+ NeuroSim: An end-to-end benchmarking framework for compute-in-memory accelerators with versatile device technologies X Peng, S Huang, Y Luo, X Sun, S Yu 2019 IEEE international electron devices meeting (IEDM), 32.5. 1-32.5. 4, 2019 | 258 | 2019 |
| Monolithically integrated RRAM-and CMOS-based in-memory computing optimizations for efficient deep learning S Yin, Y Luo, Y Kim, W He, X Han, X Sun, H Barnaby, JJ Kim, S Yu, J Seo IEEE Micro 39 (6), 54-63, 2019 | 83 | 2019 |
| RRAM for compute-in-memory: From inference to training S Yu, W Shim, X Peng, Y Luo IEEE Transactions on Circuits and Systems I: Regular Papers 68 (7), 2753-2765, 2021 | 64 | 2021 |
| Accelerating deep neural network in-situ training with non-volatile and volatile memory based hybrid precision synapses Y Luo, S Yu IEEE Transactions on Computers 69 (8), 1113-1127, 2020 | 44 | 2020 |
| MLP+ NeuroSimV3. 0: Improving on-chip learning performance with device to algorithm optimizations Y Luo, X Peng, S Yu Proceedings of the international conference on neuromorphic systems, 1-7, 2019 | 37 | 2019 |
| BEOL-compatible superlattice FEFET analog synapse with improved linearity and symmetry of weight update KA Aabrar, SG Kirtania, FX Liang, J Gomez, M San Jose, Y Luo, H Ye, ... IEEE Transactions on Electron Devices 69 (4), 2094-2100, 2022 | 33 | 2022 |
| Investigation of read disturb and bipolar read scheme on multilevel RRAM-based deep learning inference engine W Shim, Y Luo, JS Seo, S Yu IEEE Transactions on Electron Devices 67 (6), 2318-2323, 2020 | 33 | 2020 |
| Fully Coupled Multiphysics Simulation of Crosstalk Effect in Bipolar Resistive Random Access Memory S Li, W Chen, Y Luo, J Hu, P Gao, J Ye, K Kang, H Chen, E Li, WY Yin IEEE Transactions on Electron Devices 64 (9), 3647-3653, 2017 | 32 | 2017 |
| Electrothermal characterization in 3-D resistive random access memory arrays Y Luo, W Chen, M Cheng, WY Yin IEEE Transactions on Electron Devices 63 (12), 4720-4728, 2016 | 31 | 2016 |
| A Novel Scalable Energy-Efficient Synaptic Device: Crossbar Ferroelectric Semiconductor Junction M Si, Y Luo, W Chung, H Bae, D Zheng, J Li, J Qin, G Qiu, S Yu, PD Ye 2019 IEEE International Electron Devices Meeting (IEDM), 6.6. 1-6.6. 4, 2019 | 29 | 2019 |
| Array-level programming of 3-bit per cell resistive memory and its application for deep neural network inference Y Luo, X Han, Z Ye, H Barnaby, JS Seo, S Yu IEEE Transactions on Electron Devices 67 (11), 4621-4625, 2020 | 28 | 2020 |
| BEOL compatible superlattice FerroFET-based high precision analog weight cell with superior linearity and symmetry KA Aabrar, J Gomez, SG Kirtania, M San Jose, Y Luo, PG Ravikumar, ... 2021 IEEE International Electron Devices Meeting (IEDM), 19.6. 1-19.6. 4, 2021 | 27 | 2021 |
| Impact of read disturb on multilevel RRAM based inference engine: Experiments and model prediction W Shim, Y Luo, J Seo, S Yu 2020 IEEE International Reliability Physics Symposium (IRPS), 1-5, 2020 | 27 | 2020 |
| Benchmark of ferroelectric transistor-based hybrid precision synapse for neural network accelerator Y Luo, P Wang, X Peng, X Sun, S Yu IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 5 …, 2019 | 22 | 2019 |
| AILC: Accelerate on-chip incremental learning with compute-in-memory technology Y Luo, S Yu IEEE Transactions on Computers 70 (8), 1225-1238, 2021 | 18 | 2021 |
| First experimental demonstration of robust HZO/β-Ga₂O₃ ferroelectric field-effect transistors as synaptic devices for artificial intelligence applications in a high … J Noh, H Bae, J Li, Y Luo, Y Qu, TJ Park, M Si, X Chen, AR Charnas, ... IEEE Transactions on Electron Devices 68 (5), 2515-2521, 2021 | 17 | 2021 |
| A variation robust inference engine based on STT-MRAM with parallel read-out Y Luo, X Peng, R Hatcher, T Rakshit, J Kittl, MS Rodder, JS Seo, S Yu 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020 | 17 | 2020 |
| Process Development of Power Delivery Through Wafer Vias for Silicon Interconnect Fabric MH Liu, B Vaisband, A Hanna, Y Luo, Z Wan, SS Iyer 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 579-586, 2019 | 17 | 2019 |
| Robust processing-in-memory with multibit ReRAM using Hessian-driven mixed-precision computation S Dash, Y Luo, A Lu, S Yu, S Mukhopadhyay IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021 | 15 | 2021 |
| Benchmark of the compute-in-memory-based DNN accelerator with area constraint A Lu, X Peng, Y Luo, S Yu IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (9 …, 2020 | 15 | 2020 |
