Dominance-based duplication simulation (DBDS): code duplication to enable compiler optimizations D Leopoldseder, L Stadler, T Würthinger, J Eisl, D Simon, H Mössenböck Proceedings of the 2018 International Symposium on Code Generation and …, 2018 | 49 | 2018 |
Trace-based Register Allocation in a JIT Compiler J Eisl, M Grimmer, D Simon, T Würthinger, H Mössenböck Proceedings of the 13th International Conference on Principles and Practices …, 2016 | 24 | 2016 |
Trace Register Allocation Policies: Compile-time vs. Performance Trade-offs J Eisl, S Marr, T Würthinger, H Mössenböck Proceedings of the 14th International Conference on Managed Languages & Runtimes, 2017 | 12 | 2017 |
Trace Register Allocation J Eisl Universität Linz, 2018 | 9 | 2018 |
Parallel trace register allocation J Eisl, D Leopoldseder, H Mössenböck Proceedings of the 15th International Conference on Managed Languages …, 2018 | 8 | 2018 |
Trace Register Allocation J Eisl | 8 | 2015 |
Divide and Allocate: The Trace Register Allocation Framework J Eisl CGO, 2018 | 4 | 2018 |
Optimization Framework for the CACAO VM J Eisl Institute of Computer Languages, Compilers and Languages Group, TU Wien, 2013 | 1 | 2013 |
Dominance-Based Duplication Simulation (DBDS) D Leopoldseder, L Stadler, T Würthinger, J Eisl, D Simon, H Mössenböck | | 2018 |