An efficient reliable PUF-based cryptographic key generator in 65nm CMOS M Bhargava, K Mai 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014 | 141 | 2014 |
Reliability enhancement of bi-stable PUFs in 65nm bulk CMOS M Bhargava, C Cakir, K Mai 2012 IEEE International Symposium on Hardware-Oriented Security and Trust, 25-30, 2012 | 107 | 2012 |
A high reliability PUF using hot carrier injection based response reinforcement M Bhargava, K Mai Cryptographic Hardware and Embedded Systems-CHES 2013: 15th International …, 2013 | 84 | 2013 |
Attack resistant sense amplifier based PUFs (SA-PUF) with deterministic and controllable reliability of PUF responses M Bhargava, C Cakir, K Mai Hardware-Oriented Security and Trust (HOST), 2010 IEEE International …, 2010 | 68 | 2010 |
On-Chip Memory Technology Design Space Explorations for Mobile Deep Neural Network Accelerators H Li, M Bhargava, PN Whatmough, HSP Wong Proceedings of the 56th Annual Design Automation Conference 2019, 131, 2019 | 58 | 2019 |
Variation-tolerant SRAM sense-amplifier timing using configurable replica bitlines U Arslan, MP McCartney, M Bhargava, X Li, K Mai, LT Pileggi 2008 IEEE Custom Integrated Circuits Conference, 415-418, 2008 | 52 | 2008 |
Comparison of bi-stable and delay-based Physical Unclonable Functions from measurements in 65nm bulk CMOS M Bhargava, C Cakir, K Mai Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 1-4, 2012 | 44 | 2012 |
Reliability of physical unclonable function circuits KW Mai, M Bhargava US Patent App. 14/913,285, 2018 | 39 | 2018 |
6T SRAM and 3T DRAM data retention and remanence characterization in 65nm bulk CMOS C Cakir, M Bhargava, K Mai Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 1-4, 2012 | 33 | 2012 |
Low-overhead, digital offset compensated, SRAM sense amplifiers M Bhargava, MP McCartney, A Hoefler, K Mai 2009 IEEE Custom Integrated Circuits Conference, 705-708, 2009 | 33 | 2009 |
Methods for generating reliable responses in physical unclonable functions (PUFs) and methods for designing strong PUFs KW Mai, M Bhargava US Patent App. 15/128,693, 2019 | 27 | 2019 |
Memory devices formed from correlated electron materials M Bhargava, P Agarwal, A Kumar, GA Rosendale US Patent 10,002,665, 2018 | 26 | 2018 |
Reliable, Secure, Efficient Physical Unclonable Functions M Bhargava | 25 | 2013 |
Low VMIN 20nm embedded SRAM with multi-voltage wordline control based read and write assist techniques M Bhargava, YK Chong, V Schuppe, B Maiti, M Kinkade, HY Chen, ... 2014 Symposium on VLSI Circuits Digest of Technical Papers, 1-2, 2014 | 20 | 2014 |
SCAN-PUF: A low overhead Physically Unclonable Function from scan chain power-up states B Niewenhuis, RD Blanton, M Bhargava, K Mai 2013 IEEE International Test Conference (ITC), 1-8, 2013 | 20 | 2013 |
Voltage detection with correlated electron switch M Bhargava, GA Rosendale, S Das US Patent 10,352,971, 2019 | 19 | 2019 |
Method, system and device for correlated electron switch (CES) device operation M Bhargava, GA Rosendale US Patent 10,002,669, 2018 | 18 | 2018 |
Process variation compensation with correlated electron switch devices V Chandra, M Bhargava US Patent 10,267,831, 2019 | 17 | 2019 |
Virtual prototyper (ViPro) an early design space exploration and optimization tool for SRAM designers S Nalam, M Bhargava, K Mai, BH Calhoun Proceedings of the 47th Design Automation Conference, 138-143, 2010 | 17 | 2010 |
Enhanced 3D Implementation of an Arm® Cortex®-A Microprocessor X Xu, M Bhargava, S Moore, S Sinha, B Cline 2019 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2019 | 16 | 2019 |