| M-ATTEMPT: A new energy-efficient routing protocol for wireless body area sensor networks N Javaid, Z Abbas, MS Fareed, ZA Khan, N Alrajeh Procedia Computer Science 19, 224-231, 2013 | 303 | 2013 |
| Impact of technology scaling on leakage power in nano-scale bulk CMOS digital standard cells Z Abbas, M Olivieri Microelectronics Journal 45 (2), 179-195, 2014 | 68 | 2014 |
| A voltage-based leakage current calculation scheme and its application to nanoscale MOSFET and FinFET standard-cell designs Z Abbas, A Mastrandrea, M Olivieri IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (12 …, 2014 | 35 | 2014 |
| Current controlled current conveyor (CCCII) and application using 65nm CMOS technology Z Abbas, G Scotti, M Olivieri International Journal of Electronics and Communication Engineering 5 (7 …, 2011 | 35 | 2011 |
| Optimal transistor sizing for maximum yield in variation‐aware standard cell design Z Abbas, M Olivieri International Journal of Circuit Theory and Applications 44 (7), 1400-1424, 2016 | 28 | 2016 |
| Optimal NBTI degradation and PVT variation resistant device sizing in a full adder cell Z Abbas, M Olivieri, U Khalid, A Ripp, M Pronath 2015 4th International Conference on Reliability, Infocom Technologies and …, 2015 | 25 | 2015 |
| An End‐to‐End Cardiac Arrhythmia Recognition Method with an Effective DenseNet Model on Imbalanced Datasets Using ECG Signal H Ullah, MB Bin Heyat, F Akhtar, Sumbul, AY Muaad, MS Islam, Z Abbas, ... Computational Intelligence and Neuroscience 2022 (1), 9475162, 2022 | 21 | 2022 |
| A high psrr, stable cmos current reference using process insensitive tc of resistance for wide temperature applications A Jain, A Ali, S Kiran, Z Abbas 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019 | 20 | 2019 |
| AI/ML algorithms and applications in VLSI design and technology D Amuru, A Zahra, HV Vudumula, PK Cherupally, SR Gurram, A Ahmad, ... Integration 93, 102048, 2023 | 19 | 2023 |
| Experimental use of electronic nose for analysis of volatile organic compound (VOC) SH Saeed, Z Abbas, B Gopal 2009 International Multimedia, Signal Processing and Communication …, 2009 | 17 | 2009 |
| A novel logic level calculation model for leakage currents in digital nano-CMOS circuits Z Abbas, V Genua, M Olivieri 2011 7th Conference on Ph. D. Research in Microelectronics and Electronics …, 2011 | 15 | 2011 |
| A novel smart belt for anxiety detection, classification, and reduction using IIoMT on students’ cardiac signal and MSY R Pal, D Adhikari, MBB Heyat, B Guragai, V Lipari, J Brito Ballester, ... Bioengineering 9 (12), 793, 2022 | 14 | 2022 |
| Robust transistor sizing for improved performances in digital circuits using optimization algorithms P Gupta, H Mandadapu, S Gourishetty, Z Abbas 20th International Symposium on Quality Electronic Design (ISQED), 85-91, 2019 | 13 | 2019 |
| A 9.5 nW, 0.55 V supply, CMOS current reference for low power biomedical applications S Agarwal, A Pathy, Z Abbas IEEE Transactions on Circuits and Systems II: Express Briefs 69 (9), 3650-3654, 2022 | 12 | 2022 |
| An efficient gradient boosting approach for PVT aware estimation of leakage power and propagation delay in CMOS/FinFET digital cells D Amuru, MS Ahmed, Z Abbas 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020 | 12 | 2020 |
| A sub-nw, 8t current reference consuming constant power wrt process & temperature A Ali, A Pullela, A Jain, Z Abbas 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems …, 2020 | 12 | 2020 |
| Pvt variations aware robust transistor sizing for power-delay optimal cmos digital circuit design P Gupta, S Gourishetty, H Mandadapu, Z Abbas 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019 | 12 | 2019 |
| Yield-driven power-delay-optimal CMOS full-adder design complying with automotive product specifications of PVT variations and NBTI degradations Z Abbas, M Olivieri, A Ripp Journal of Computational Electronics 15, 1424-1439, 2016 | 12 | 2016 |
| Statistical variation aware leakage and total power estimation of 16 nm vlsi digital circuits based on regression models D Amuru, A Zahra, Z Abbas VLSI Design and Test: 23rd International Symposium, VDAT 2019, Indore, India …, 2019 | 10 | 2019 |
| Design centering/yield optimization of power aware band pass filter based on CMOS current controlled current conveyor (CCCII+) Z Abbas, M Olivieri, M Yakupov, A Ripp Microelectronics Journal 44 (4), 321-331, 2013 | 10 | 2013 |
Mauro OlivieriSapienza University of Rome, Italy. - Barcelona Supercomputing Center, Spain.在 uniroma1.it 的电子邮件经过验证
