Abstractions for model checking SDN controllers D Sethi, S Narayana, S Malik 2013 Formal Methods in Computer-Aided Design, 145-148, 2013 | 59 | 2013 |
SAT-based techniques for determining backbones for post-silicon fault localisation CS Zhu, G Weissenbacher, D Sethi, S Malik 2011 IEEE International High Level Design Validation and Test Workshop, 84-91, 2011 | 44 | 2011 |
Topology explorer D Sethi, C Nagarajan, RR Kompella, G Gupta, S Iyer US Patent 10,498,608, 2019 | 41 | 2019 |
Handling controller and node failure scenarios during data collection C Nagarajan, D Sethi, RR Kompella US Patent 10,574,513, 2020 | 34 | 2020 |
Synthesis of models for networks using automated boolean learning D Sethi, C Nagarajan US Patent 10,826,770, 2020 | 14 | 2020 |
Collecting network models and node information from a network C Nagarajan, D Sethi, RR Kompella US Patent 10,686,669, 2020 | 10 | 2020 |
Specification and synthesis of hardware checkpointing and rollback mechanisms C Chan, D Schwartz-Narbonne, D Sethi, S Malik Proceedings of the 49th Annual Design Automation Conference, 1226-1232, 2012 | 8 | 2012 |
Using flow specifications of parameterized cache coherence protocols for verifying deadlock freedom D Sethi, M Talupur, S Malik Automated Technology for Verification and Analysis: 12th International …, 2014 | 7 | 2014 |
Epoch comparison for network policy differences C Nagarajan, D Sethi, S Harneja, DH Jain, CJ Lo US Patent App. 16/225,831, 2020 | 6 | 2020 |
Model checking unbounded concurrent lists D Sethi, M Talupur, S Malik International Journal on Software Tools for Technology Transfer 18, 375-391, 2016 | 6 | 2016 |
Check-pointing ACI network state and re-execution from a check-pointed state D Sethi, C Nagarajan, A Dixit, JT Monk, GC Ng, RR Kompella, S Iyer US Patent 10,873,509, 2020 | 5 | 2020 |
Parameterized model checking of fine grained concurrency D Sethi, M Talupur, D Schwartz-Narbonne, S Malik Model Checking Software: 19th International Workshop, SPIN 2012, Oxford, UK …, 2012 | 5 | 2012 |
Address translation for external network appliance V Balamurugan, C Nagarajan, D Sethi, C Velpula, V Manvesh, ... US Patent 11,909,713, 2024 | 1 | 2024 |
Specification and encoding of transaction interaction properties D Sethi, Y Mahajan, S Malik Formal Methods in System Design 39, 144-164, 2011 | 1 | 2011 |
Check-pointing ACI network state and re-execution from a check-pointed state D Sethi, C Nagarajan, A Dixit, JT Monk, GC Ng, RR Kompella, S Iyer US Patent 11,824,728, 2023 | | 2023 |
Topology explorer D Sethi, C Nagarajan, RR Kompella, G Gupta, S Iyer US Patent 11,463,316, 2022 | | 2022 |
Address translation for external network appliance V Balamurugan, C Nagarajan, D Sethi, C Velpula, V Manvesh, ... US Patent 11,019,027, 2021 | | 2021 |
Assurance of quality-of-service configurations in a network C Nagarajan, K Mohanram, RR Kompella, D Sethi, S Iyer US Patent 10,826,788, 2020 | | 2020 |
Scaling Verification by Leveraging Parametrization D Sethi Princeton University, 2014 | | 2014 |
Specification and Encoding of Transaction Interaction Properties in Transaction-Based Models D Sethi, S Malik Poster, GSRC Annual Symposium 3, 2009 | | 2009 |