| A 500 kS/s 8-bit charge recycle based 2-bit per step SAR-ADC P Shrivastava, KG Bhat, T Laxminidhi, MS Bhat 2012 Third International Conference on Emerging Applications of Information …, 2012 | 9 | 2012 |
| A compact 10-bit nonbinary weighted switched capacitor integrator based SAR ADC architecture KG Bhat, T Laxminidhi, MS Bhat 2019 IEEE Asia Pacific Conference on Postgraduate Research in …, 2019 | 3 | 2019 |
| Resolution-independent fully differential SCI-based SAR ADC architecture using six unit capacitors KG Bhat, T Laxminidhi, MS Bhat Sādhanā 45, 1-4, 2020 | 2 | 2020 |
| An 8-b 1.5 MS/s 2-bit per cycle SAR ADC with parasitic insensitive single capacitive reference DAC KG Bhat, T Laxminidhi, MS Bhat TENCON 2015-2015 IEEE Region 10 Conference, 1-6, 2015 | 1 | 2015 |
| Low Power Nonbinary Weighted Successive Approximation Register Analog to Digital Converters KG Bhat National Institute of Technology Karnataka, Surathkal, 2021 | | 2021 |
| A compact 4-to-8-bit nonbinary SAR ADC based on 2 bits per cycle DAC architecture KG Bhat, T Laxminidhi, MS Bhat Sādhanā 44, 1-11, 2019 | | 2019 |
