| An approach for complete 2-D analytical potential modelling of fully depleted symmetric double gate junction less transistor K Chandra Deva Sarma, S Sharma Journal of Computational Electronics 14, 717-725, 2015 | 27 | 2015 |
| A method for reduction of off state leakage current in symmetric DG JLT KCD Sarma, S Sharma Engineering Research Express 1 (1), 015034, 2019 | 11 | 2019 |
| A method for determination of depletion width of single and double gate junction less transistor KCD Sarma, S Sharma 2015 International Conference on Electronic Design, Computer Networks …, 2015 | 11 | 2015 |
| Dependence of Electrical Characteristics of Junctionless FET on Body Material KCDS Angshumala Talukdar, Apurba Kumar Raibaruah procedia computer science 171 (6), 1046-1053, 2020 | 8 | 2020 |
| A potential model for parallel gated junctionless field effect transistor AK Raibaruah, KCD Sarma Silicon, 1-8, 2022 | 5 | 2022 |
| Surrounded Channel Junctionless Field Effect Transistor N Das, KCD Sarma 2020 International Conference on Computational Performance Evaluation (ComPE …, 2020 | 5 | 2020 |
| Behavioural Design and Synthesis of 64 BIT ALU using Xilinx ISE R Chetia, KCD Sarma, G Baruah IOSR Journal of Electronics and Communication Engineering (IOSRJECE) ISSN …, 2013 | 5 | 2013 |
| Parallel gated junctionless field effect transistor AK Raibaruah, KCD Sarma 2020 International conference on computational performance evaluation (ComPE …, 2020 | 4 | 2020 |
| Carrier Mobility Enhancement of Symmetric Double Gate Junctionless Transistor SS KCD Sarma Journal of Nanoelectronics and Optoelectronics 12 (10), 1084-1092, 2017 | 3 | 2017 |
| Study on Electrical Characteristics of Double gate Junctionless Field Effect Transistor With Triangle Shaped Spacer A Baro, KCD Sarma 2020 International Conference on Computational Performance Evaluation (ComPE …, 2020 | 2 | 2020 |
| Undoped Junctionless Field Effect Transistor AK Raibaruah, A Talukdar, KCD Sarma 2020 International Conference on Computational Performance Evaluation (ComPE …, 2020 | 2 | 2020 |
| An analytical approach for drain current modelling of a symmetric double gate junctionless transistor S Sharma, KCD Sarma Journal of Nanoelectronics and Optoelectronics 13 (9), 1332-1339, 2018 | 2 | 2018 |
| Channel Potential Modelling of Surrounded Channel Junction Less Field Effect Transistor N Das, KC Deva Sarma Journal of Nanoelectronics and Optoelectronics 17 (2), 211-217, 2022 | 1 | 2022 |
| Threshold Voltage and Flat Band Voltage of Normally on Junction Less Field Effect Transistor A Talukdar, KC Deva Sarma Journal of Nanoelectronics and Optoelectronics 17 (1), 100-103, 2022 | 1 | 2022 |
| An Analytical Potential Model for Normally on Double Gate Junctionless Field Effect Transistor KCDS Angshumala Talukdar International Conference on Computational Performance Evaluation (ComPE …, 2020 | 1* | 2020 |
| Depletion Width Modelling of Surrounded Channel Junctionless Field Effect Transistor N Das, KCD Sarma 2020 International Conference on Computational Performance Evaluation (ComPE …, 2020 | 1 | 2020 |
| Scale length determination of Gate all around (Octagonal cross section) Junctionless Transistor KCD Sarma, S Sharma 2015 International Conference on Electronic Design, Computer Networks …, 2015 | 1 | 2015 |
| Scale length determination of a fully depleted surrounding gate (rectangular cross section) junction less transistor KCD Sarma, S Sharma, C Hazarika 2015 International Conference on Electrical, Electronics, Signals …, 2015 | 1 | 2015 |
| Study of performance evaluation of various characteristics of a single phase full bridge inverter circuit using surrounded channel junctionless field effect transistor N Das, KCD Sarma Discover Electronics 1 (1), 1-10, 2024 | | 2024 |
| Study on performance Evaluation of CMOS Inverter using Surrounded channel Junctionless Field Effect Transistor N Das, KCD Sarma | | 2023 |
Santanu SharmaProfessor, Department of ECE, Tezpur University在 tezu.ernet.in 的电子邮件经过验证
