受强制性开放获取政策约束的文章 - Atanu Kundu了解详情
无法在其他位置公开访问的文章：8 篇
Influence of Underlap on Gate Stack DG-MOSFET for analytical study of Analog/RF performance
A Kundu, A Dasgupta, R Das, S Chakraborty, A Dutta, CK Sarkar
Superlattices and Microstructures 94, 60-73, 2016
强制性开放获取政策： Council of Scientific and Industrial Research, India, Department of Science …
Subthreshold analog/RF performance of underlap DG FETs with asymmetric source/drain extensions
K Koley, B Syamal, A Kundu, N Mohankumar, CK Sarkar
Microelectronics Reliability 52 (11), 2572-2578, 2012
强制性开放获取政策： Department of Science & Technology, India
Impact of gate metal work-function engineering for enhancement of subthreshold analog/RF performance of underlap dual material gate DG-FET
A Kundu, K Koley, A Dutta, CK Sarkar
Microelectronics Reliability 54 (12), 2717-2722, 2014
强制性开放获取政策： Council of Scientific and Industrial Research, India, Department of Science …
Comparisons between dual and tri material gate on a 32 nm double gate MOSFET
A Dasgupta, R Das, S Chakraborty, A Dutta, A Kundu, CK Sarkar
Nano 11 (10), 1650117, 2016
强制性开放获取政策： Department of Science & Technology, India
An optimisation based study of underlap architecture of sub 16 nm double gate MOSFET for enhanced analog performance
R Das, P Pandit, S Chakraborty, A Dasgupta, A Kundu, CK Sarkar
Materials Focus 6 (3), 305-309, 2017
强制性开放获取政策： Council of Scientific and Industrial Research, India, Department of Science …
A comparative study of analog/RF performance: symmetric and asymmetric underlap gate stack DG-MOSFETs
A Dasgupta, R Das, A Dutta, A Kundu, CK Sarkar
2016 3rd International Conference on Devices, Circuits and Systems (ICDCS …, 2016
强制性开放获取政策： Department of Science & Technology, India
Asymmetric underlap dual Material Gate DG-FET for low power analog/RF applications
A Kundu, A Dutta, CK Sarkar
Journal of Low Power Electronics 11 (4), 509-516, 2015
强制性开放获取政策： Council of Scientific and Industrial Research, India, Department of Science …
Analog/RF performance comparison of underlap gate stack DG NMOSFETs in sub 65nm regime
P Pandit, N Rakshit, S Chakraborty, M Dutta, A Kundu
2017 Devices for Integrated Circuit (DevIC), 594-598, 2017
强制性开放获取政策： Council of Scientific and Industrial Research, India, Department of Science …
可在其他位置公开访问的文章：3 篇
Influence on the analog/RF performance in graded channel Gate Stack DG-MOSFETs
A Chattopadhyay, A Dutta, A Kundu, CK Sarkar
2016 3rd International Conference on Devices, Circuits and Systems (ICDCS …, 2016
强制性开放获取政策： Department of Science & Technology, India
An RF Based Optimization of Underlap of Sub 16 nm Double Gate MOSFET
P Pandit, R Das, S Chakraborty, A Dasgupta, A Kundu, CK Sarkar
Advances in Industrial Engineering and Management 6 (1), 6-10, 2017
强制性开放获取政策： Council of Scientific and Industrial Research, India, Department of Science …
RF parameter extraction of underlap DG MOSFETs: a look up table based approach
A Kundu, A Dutta, K Koley, S Niyogi, CK Sarkar
IET Circuits, Devices & Systems 8 (6), 554-560, 2014
强制性开放获取政策： Council of Scientific and Industrial Research, India, Department of Science …
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