| Another trip to the wall: How much will stacked dram benefit hpc? M Radulovic, D Zivanovic, D Ruiz, BR de Supinski, SA McKee, ... Proceedings of the 2015 International Symposium on Memory Systems, 31-36, 2015 | 59 | 2015 |
| Main memory in HPC: Do we need more or could we live with less? D Zivanovic, M Pavlovic, M Radulovic, H Shin, J Son, SA Mckee, ... ACM Transactions on Architecture and Code Optimization (TACO) 14 (1), 1-26, 2017 | 53 | 2017 |
| Cost-aware prediction of uncorrected DRAM errors in the field I Boixaderas, D Zivanovic, S Moré, J Bartolome, D Vicente, M Casas, ... SC20: International Conference for High Performance Computing, Networking …, 2020 | 25 | 2020 |
| DRAM errors in the field: A statistical approach D Zivanovic, PE Dokht, S Moré, J Bartolome, PM Carpenter, P Radojković, ... Proceedings of the International Symposium on Memory Systems, 69-84, 2019 | 12 | 2019 |
| Large-memory nodes for energy efficient high-performance computing D Zivanovic, M Radulovic, G Llort, D Zaragoza, J Strassburg, ... Proceedings of the Second International Symposium on Memory Systems, 3-9, 2016 | 8 | 2016 |
| Mainstream vs. emerging HPC: Metrics, trade-offs and lessons learned M Radulovic, K Asifuzzaman, D Zivanovic, N Rajovic, GC de Verdiere, ... 2018 30th International Symposium on Computer Architecture and High …, 2018 | 4 | 2018 |
| Architecture and implementation of modular wireless sensor network node VB Kovac̆ević, D Z̆ivanović, M Nikolić, Z Stojković Proceedings of Papers 5th European Conference on Circuits and Systems for …, 2010 | 3 | 2010 |
