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Sandeep Semwal
Sandeep Semwal
Ph.D scholar
在 iiti.ac.in 的电子邮件经过验证
标题
引用次数
引用次数
年份
Limits on hysteresis-free sub-60 mV/decade operation of MFIS nanowire transistor
S Semwal, VP Reddy, N Jaiswal, A Kranti
IEEE Transactions on Electron Devices 67 (9), 3868-3875, 2020
152020
Unconventional VTC of subthreshold inverter with MFMIS negative capacitance transistor: An analytical modelling framework with implications for ultralow power logic design
S Semwal, A Kranti
Semiconductor Science and Technology 37 (6), 065012, 2022
82022
Insights into unconventional behaviour of negative capacitance transistor through a physics-based analytical model
S Semwal, A Kranti
Semiconductor Science and Technology 36 (9), 095018, 2021
82021
An insightful assessment of 1T-DRAM with misaligned polarity gate in RFET
AS Roy, S Semwal, A Kranti
IEEE Transactions on Electron Devices 69 (6), 3163-3168, 2022
62022
A critique of length and bias dependent constraints for 1T-DRAM operation through RFET
RK Nirala, S Semwal, A Kranti
Semiconductor Science and Technology 37 (10), 105013, 2022
52022
Improved mobility extraction methodology for reconfigurable transistors considering resistive components and effective drain bias
S Mane, S Semwal, A Kranti
IEEE Transactions on Electron Devices 68 (9), 4797-4800, 2021
52021
Incorporating quantum effects in ultralow power (ULP) subthreshold logic design with junctionless nanowire transistor
N Rai, K Ahuja, S Semwal, A Kranti
IEEE Transactions on Electron Devices 69 (7), 3983-3989, 2022
42022
Architectural evaluation of programmable transistor-based capacitorless DRAM for high-speed system-on-chip applications
RK Nirala, AS Roy, S Semwal, N Rai, A Kranti
Japanese Journal of Applied Physics 62 (SC), SC1040, 2023
32023
Analytical modeling of negative capacitance transistor based ultra low power Schmitt trigger
G Keerthi, S Semwal, A Kranti
Solid-State Electronics 207, 108700, 2023
22023
A metal–ferroelectric–insulator–semiconductor transistor perspective: Nanowire or planar architecture?
S Semwal, A Kranti
Journal of Materials Research 36, 3484-3494, 2021
22021
Ultra-low-power subthreshold logic with germanium junctionless transistors
P Shrivas, N Jaiswal, S Semwal, A Kranti
Semiconductor Science and Technology 36 (7), 075011, 2021
22021
Analytical model for quasi-ballistic transport in MOSFET including carrier backscattering
S Semwal, S Agrawal, A Srivastava, G Kaushal
Journal of Computational Electronics 20, 838-847, 2021
22021
Pragmatic Evaluation of Process Corners in ULP Subthreshold Circuits With Quantum Confinement Effects in Junctionless Nanowire Transistor
N Rai, S Semwal, RK Nirala, A Kranti
IEEE Transactions on Circuits and Systems I: Regular Papers, 2023
12023
Sensitivity implications for programmable transistor based 1T-DRAM
RK Nirala, S Semwal, YV Bhuvaneshwari, N Rai, A Kranti
Solid-State Electronics 194, 108353, 2022
12022
Extremely High Noise Margin and Low Leakage in ULP Circuits with NCFETs
S Semwal, RK Nirala, M Gupta, A Kranti
2024 International VLSI Symposium on Technology, Systems and Applications …, 2024
2024
Energy and Disturbance Analysis of 1T-DRAM With Nanowire Gate-All-Around RFET
RK Nirala, S Semwal, M Gupta, A Kranti
IEEE Transactions on Electron Devices, 2024
2024
Quantum Confinement Imposed Constraints in ULP Circuits with Junctionless FET
S Semwal, N Rai, RK Nirala, M Gupta, A Kranti
2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 1-3, 2024
2024
Insights Into Parasitic Capacitance and Reconfigurable FET Architecture for Enhancing Analog/RF Metrics
AA Deshpande, S Semwal, JP Raskin, A Kranti
IEEE Transactions on Electron Devices, 2023
2023
Analytical modeling of architecture dependent atypical scaling trends in metal–Hf0. 5Zr0. 5O2–metal-SiO2–Si negative capacitance transistors
S Semwal, A Kranti
Semiconductor Science and Technology 38 (9), 095011, 2023
2023
Architecture Dependent Constraint-Aware RFET Based 1T-DRAM
S Semwal, RK Nirala, N Rai, A Kranti
2023 International VLSI Symposium on Technology, Systems and Applications …, 2023
2023
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