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Yongwoo Jo
Yongwoo Jo
Electrical Engineering, KAIST
在 kaist.ac.kr 的电子邮件经过验证
标题
引用次数
引用次数
年份
An external capacitorless low-dropout regulator with high PSR at all frequencies from 10 kHz to 1 GHz using an adaptive supply-ripple cancellation technique
Y Lim, J Lee, S Park, Y Jo, J Choi
IEEE Journal of Solid-State Circuits 53 (9), 2675-2685, 2018
842018
17.8 A 170MHz-Lock-In-Range and −253dB-FoMjitter 12-to-14.5GHz Subsampling PLL with a 150µW Frequency-Disturbance-Correcting Loop Using a Low-Power …
Y Lim, J Kim, Y Jo, J Bang, S Yoo, H Park, H Yoon, J Choi
2020 IEEE International Solid-State Circuits Conference-(ISSCC), 280-282, 2020
212020
A 104fsrms-Jitter and-61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique
J Kim, Y Jo, Y Lim, T Seong, H Park, S Yoo, Y Lee, S Choi, J Choi
2021 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC) 64, 448-+, 2021
162021
An Ultra-Low-Jitter 22.8-GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier With a Multiplication Factor of 114
S Choi, S Yoo, Y Lee, Y Jo, J Lee, Y Lim, J Choi
IEEE Journal of Solid-State Circuits 54 (4), 927-936, 2018
142018
A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier
Y Jo, J Kim, Y Shin, H Park, C Hwang, Y Lim, J Choi
IEEE Journal of Solid-State Circuits, 2023
122023
A 135fsrms-Jitter 0.6-to-7.7GHz LO Generator Using a Single LC-VCO-Based Subsampling PLL and a Ring-Oscillator-Based Sub-Integer-N Frequency Multiplier
Y Jo, J Kim, Y Shin, C Hwang, H Park, J Choi
2023 IEEE International Solid-State Circuits Conference (ISSCC), 1-3, 2023
102023
A wide-lock-in-range and low-jitter 12–14.5 GHz SSPLL using a low-power frequency-disturbance-detecting and correcting loop
Y Lim, J Kim, Y Jo, J Bang, J Choi
IEEE Journal of Solid-State Circuits 57 (2), 480-491, 2021
102021
32.4 A 104fsrms-Jitter and -61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique
J Kim, Y Jo, Y Lim, T Seong, H Park, S Yoo, Y Lee, S Choi, J Choi
2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 448-450, 2021
102021
A 12.8–15.0-GHz Low-Jitter Fractional- Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation
J Kim, Y Jo, H Park, T Seong, Y Lim, J Choi
IEEE Journal of Solid-State Circuits, 2023
52023
153 FSRMS-Integrated-Jitter and 114-Multiplication Factor PVT-Robust 22.8 GHZ Ring-LC-Hybrid Injection-Locked Clock Multiplier
S Choi, S Yoo, Y Lee, Y Jo, J Lee, Y Lim, J Choi
2018 IEEE Symposium on VLSI Circuits, 185-186, 2018
42018
28.5 A 900µW, 1-4GHz Input-Jitter-Filtering Digital-PLL-Based 25%-Duty-Cycle Quadrature-Clock Generator for Ultra-Low-Power Clock Distribution in High-Speed …
Y Shin, Y Jo, J Kim, J Lee, J Kim, J Choi
2023 IEEE International Solid-State Circuits Conference (ISSCC), 408-410, 2023
32023
10.5 A 76 fsrms- Jitter and -65dBc- Fractional-Spur Fractional-N Sampling PLL Using a Nonlinearity-Replication Technique
Y Shin, J Lee, J Kim, Y Jo, J Choi
2024 IEEE International Solid-State Circuits Conference (ISSCC) 67, 196-198, 2024
12024
A Digital-PLL-Based Quadrature Clock Generator for a Low-Power and Jitter-Filtering-Capable Clock Distribution Scheme in High-Speed DRAM Interfaces
Y Shin, Y Jo, J Kim, J Lee, J Kim, J Choi
IEEE Journal of Solid-State Circuits, 2024
2024
Integrated circuit devices having enhanced clock generators therein
J Choi, Y Shin, J Kim, JO Yongwoo
US Patent App. 18/347,920, 2024
2024
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