SeVNoC: Security validation of system-on-chip designs with NoC fabrics X Meng, K Raj, S Ray, K Basu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2022 | 8 | 2022 |
Soccom: Automated synthesis of system-on-chip architectures APD Nath, K Raj, S Bhunia, S Ray IEEE Transactions on Very Large Scale Integration (VLSI) Systems 30 (4), 449-462, 2022 | 8 | 2022 |
SoCCAR: Detecting system-on-chip security violations under asynchronous resets X Meng, K Raj, APD Nath, K Basu, S Ray 2021 58th ACM/IEEE Design Automation Conference (DAC), 625-630, 2021 | 5 | 2021 |
The curious case of trusted IC provisioning in untrusted testing facilities S Ray, AP Deb Nath, K Raj, S Bhunia Proceedings of the 2021 on Great Lakes Symposium on VLSI, 207-212, 2021 | 3 | 2021 |
SSEL: An Extensible Specification Language for SoC Security K Raj, A Hegde, APD Nath, S Bhunia, S Ray 2021 Asian Hardware Oriented Security and Trust Symposium (AsianHOST), 1-6, 2021 | 2 | 2021 |
Establishing trust in untrusted IC testing and provisioning environment S Bhunia, APD Nath, K Raj, S Ray, PSL Sriramakumara US Patent 11,899,827, 2024 | 1 | 2024 |
Trimming The Fat: A Minimum-Security Architecture for Protecting SoC Designs Against Supply Chain Threats K Raj, A Bhattacharyay, S Bhunia, S Ray 2024 25th International Symposium on Quality Electronic Design (ISQED), 1-1, 2024 | | 2024 |
System-On-Chip Information Flow Validation Under Asynchronous Resets SS Miftah, K Raj, X Meng, S Ray, K Basu IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024 | | 2024 |
CASTLE: Architecting Assured System-on-Chip Firmware Integrity S Ray, APD Nath, K Raj, S Bhunia 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2021 | | 2021 |